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Laboratoire de lAccélérateur Linéaire (IN2P3-CNRS) Orsay, France LHCb upgrade meeting Packing Chiche Ronic Caceres Thierry Duarte Olivier.

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Presentation on theme: "Laboratoire de lAccélérateur Linéaire (IN2P3-CNRS) Orsay, France LHCb upgrade meeting Packing Chiche Ronic Caceres Thierry Duarte Olivier."— Presentation transcript:

1 Laboratoire de lAccélérateur Linéaire (IN2P3-CNRS) Orsay, France LHCb upgrade meeting Packing Chiche Ronic Caceres Thierry Duarte Olivier

2 Olivier Duarte LHCb upgrade meeting 2 Schedule for SPECS development CROC prototype tests : schedule Data flow and firmware architecture BXId 12 1 byte February 11th 2011 ADC 12 A3PE1500 FPGA BXId and Energy calculation Energy Mapping 8 Shorts ADC 1 byte 5 bytes2 bytes 2 long ADC 8 to 16 Data compression Data register Mux Buffer RAM Packing Optical link GBT Multi-Gb/s Data Transmission Output data format : Buffer RAM Event counter (350) Formatting ADC datas (pipeline)

3 Olivier Duarte LHCb upgrade meeting 3 Schedule for SPECS development CROC prototype tests : schedule Firmware architecture and data size February 11th 2011 (x8) ADC Short 12 Packing Comparator Long Mapping Shift BXId and Energy calculation BXId 1 byte Energy Mapping 8 Shorts ADC 1 byte 5 bytes0 to 8 bytes long ADC 8 to 16 Short (5 bit) Pedestal -8 Pedestal +23 Long (12 bit) Comparator Formatting ADC datas

4 Olivier Duarte Firmware : data flow packing proposal LHCb upgrade meeting 4 February 11th Circular buffer (32 x 8 bits) State 80Mhz P : Wr pointer N : length word I : Rd pointer P I 10 bytes register RAM buffer BXId 1 byte Energy Mapping 8 Shorts ADC 1 byte 5 bytes0 to 8 bytes long ADC N = 8 to 16 bytes 10 RAM buffer Formatting ADC datas Event Data flow Mux GBT Mux 40Mhz 80Mhz 40Mhz PNPN I N P N-1 P N Events ? Data ?

5 Olivier Duarte Firmware : State Machine - Rd/Wr circular buffer - Wr RAM buffer, Rd ? LHCb upgrade meeting 5 February 11th 2011 t0t0 t1t1 t2t2 t3t3 t4t4 Idle - Rd de la longueur du mot N - Wr du mot de longueur N dans buffer circulaire - Calcul de S = P + N – I comparé à 10, 20; Avec P : Pointeur de Wr N : Longueur du mot Wr I : pointeur de Rd S S 20 S 20 Start Acq Stop Acq - Lecture de 10 bytes du buffer circulaire - Increment (I + 10) - Lecture de 2x 10 bytes du buffer circulaire - Increment (I + 20) Clock state machine 80 Mhz Clock event 40 Mhz Calcul " longueur doccupation S "

6 Olivier Duarte LHCb upgrade meeting 6 SPARE December 10th 2010

7 Olivier Duarte LHCb upgrade meeting 7 Schedule for SPECS development CROC prototype tests : schedule ADC comparator to short, long February 11th 2011 Short (5 bit) Pedestal Pedestal -8 Pedestal +23 Long (12 bit) t0t0 t1t1 t2t2 t3t3 t4t4 S = P + N – I S S 20 S 20 Start Acq Stop Acq Rd 10 bytes (I + 10) Rd 20 bytes (I + 20)


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