1. Design and Scaling of SiGe BiCMOS VCOs Above 100GHz
S. T. Nicolson1, K.H.K Yau1, K.A. Tang1, P. Chevalier2, A. Chantre2 B. Sautreuil2, and S. P. Voinigescu1
1) Edward S. Rogers Sr. Dept. of Elec. & Comp. Eng., Univ. of Toronto
2) STMicroelectronics

2. Outline Motivation for W-band SiGe integrated circuits
VCO design methodology for low phase noise in W-band
Layout considerations
Measurement results
Conclusions and future work

3. Motivation for W-band SiGe ICs
Typical applications: 77GHz auto radar, 94GHz weather radar, imaging
Central to these applications is the low phase noise VCO
Process development: NFmin, Rn & Ysopt difficult to measure in W-band
Use VCO as a process monitor for the noise performance of SiGe technologies
Explore VCO scaling/yield in SiGe
Under imaging, mention: security, medical, passive, also mention that applications are few – we need to be creative in finding new ones!
We are using the LC-VCO as a process monitor, kind of like the ring oscillator is used.

4. Add negative Miller capacitors Differential tuning
VCO Topology CM
VCC LB
Cext
Cvar Q1
VTUNE+
VTUNE-
LEE
REE
CEE LC
VBB
2.5 V
No cascode
lower phase noise, lower supply voltage
Colpitts topology
maximize fosc relative to other topologies
Augment Cbe with Cext
Reduces phase noise
Add negative Miller capacitors
Increases fosc by cancelling Cm
Differential tuning
reduces supply induced noise
24mA
VTUNE
Stress single design and layout, with differing technologies (emitter width and layers). Minimal possible differences between VCOs in vastly different technologies. RB rp cp
bib E C B
Cext

5. W-Band VCO Design Methodology
Use smallest realizable LB with adequate Q
Given fosc, maximize tuning range using large Cext
Negative resistance
Phase noise formula
Phase noise trade-off when HBT pushed to limit
Minimize HBT noise  bias at NFmin current density
Maximize Vtank and Cext bias at peak fT current density
Max. Rneg occurs at peak fT/fMAX bias
Since the technologies have the same BEOL, the only tech. dependent design step is finding NFmin bias. This is easily adjusted during testing by means of a DC control voltage.

6. VCO Fabrication Fabricated in three technology splits:
All VCO layouts and bias currents are identical – no redesign
Directly compare VCOs fabricated in different processes
Use the VCO to optimize HBT profile
Noise parameters from phase noise
fMAX from VCO output power
BiC9 fT = 150GHz fMAX = 160GHz
emitter 4×5mm×0.17mm
BipX fT = 230GHz fMAX = 300GHz
emitter 4×5mm×0.13mm
BipX1 fT = 270GHz fMAX = 260GHz
emitter 4×5mm×0.13mm
Stress single design and layout, with differing technologies (emitter width and layers). Minimal possible differences between VCOs in vastly different technologies.

7. VCO Layout VCO core area: 100mm × 100mm
Spiral inductors where necessary to reduce area
Plenty of supply decoupling (MiM and metal-metal)
70mm
100mm

8. Technology Overview – fT/fMAX Scaling
Peak fT/fMAX current density increases at each technology node
0.17mm SiGe JpeakfT = 7mA/mm2 where fT = 150GHz
0.13mm SiGe JpeakfT = 14mA/mm2 where fT = 230GHz (or 250GHz)
Contrast with CMOS…
JpfT = 0.3mA/mm, JpfMAX = 0.2mA/mm, JNFmin = 0.15mA/mm for nm nodes
Need a plot showning fmax and ft as functions of current density for BiC9, BipX, and BipXF. Make sure that the pfT and pfMAX values agree with the paper and presentation text! fT increase by sqrt(2), JpfT doubles.

9. Measurement Results VCO performance comparison in 3 SiGe technologies
Phase noise performance
Temperature testing
Wafer mapping

10. Performance Comparison Across Technology
BiCMOS9 MOS var.
BiCMOS9 HBT var.
BipX HBT var.
BipX1 HBT var.
Tech. fT/fMAX
(GHz)
150/160
230/300
250/260
Differential Pout (dBm)
+0.7
-1.3
+2.7
+2.5
SSB 1MHz (dBc/Hz)
-101.6
-80
-98
-101.3
Osc. Freq. (GHz) 96
100
106
104
LC-oscillator frequency insensitive to technology fT/fMAX
MOS varactors give less phase noise than HBT (CBC) varactors
Higher fMAX  more output power, higher frequency
BipX1 results in lowest phase noise
State when presenting that this is an issue in CMOS too, because fT and fMAX are so layout dependent. This proves that you have to optimize the transistor layout and metallization for both fT and fMAX.

11. Phase Noise Performance
Oscillation frequency of 104GHz
Phase noise of 1MHz offset
Phase Noise in W-Band SiGe VCOs
FMCW modulation
Averaged Spectral Plot
Point out we’re claiming best phase noise, not necessarily best FOM – we’ll talk about that later.
**References provided in abstract**

12. Biasing W-Band VCOs for Low Noise
NFmin current density scales with technology and fosc
Emitter width JNFmin (scales with JpeakfT)
Frequency JNFmin (gets closer to JpeakfT)
Noise correlation further increases JNFmin [K. Yau, SiRF, 2006] cp
bib C RB E B
<inB>
<inC>
The B and C shot noise currents are correlated
Need to say something on this slide about WHY JNFmin goes higher with tech. and freq.
How exactly were the NFmin curves generated???????  from measured Y parameters  how is this done? Read Ken’s paper!

13. Phase Noise Performance Across Bias
What is the minimum phase noise current density in W-band VCOs?
Measure output power and phase noise w.r.t current density (vary VBB)
Looks like phase noise is minimum at peak fT current density
phase noise
JNFMIN increases
with frequency
output power CM
VCC LB
Cext
Cvar Q1
VTUNE+
VTUNE-
LEE
REE
CEE LC
VBB
2.5 V

14. W-Band Manufacturability Challenges
Manufacturability specifications for automotive radar are stringent
Outdoors  wide temperature variations
Must last for car’s lifetime
Low cost per part requires high yield
Is SiGe on the way to meeting such challenges?
25ºC
70ºC
50ºC
125ºC
BiC9
MOS var.
HBT var.
BipX

15. Wafer Mapping – BiCMOS9 Tested 120 VCOs on 4 wafers
Summary of BiC9 VCOs with MOS varactors (60 dice averaged)
Summary of BiC9 VCOs with HBT varactors (60 dice averaged)
4 VCOs had significantly below average performance (outliers)
2 of the 4 outlier VCOs failed to oscillate entirely
Wafer 1 2 3 4
Center freq. (GHz)
94.7
94.9
95.0
Tuning range (GHz)
4.6
Output power (dBm)
0.2
0.7
0.6
0.8
DC power (mW)
133.8
133.2
137.3
132.6
Wafer 1 2 3 4
Center freq. (GHz)
99.6
100.5
100.1
Tuning range (GHz)
3.4
3.6
3.7
Output power (dBm)
-1.1 -1
-1.4
-0.9
DC power (mW)
133.0
136.2
132.8

16. Wafer Mapping – BipX Oscillation Frequency Phase Noise at 1MHz offset
VCO not present
Die not tested
< -98 dBc/Hz
-95 – -98 dBc/Hz
-92 – -95 dBc/Hz
> -92 dBc/Hz
Oscillation Frequency
Phase Noise at 1MHz offset
GHz
GHz
GHz
GHz
Wafer flat
Location of VCO in reticule

17. Figures of Merit
Comparison of our work to other state of the art W-Band VCOs
References [1] Huang P. et al, ISSCC [2] Kobayashi K. W. et al, JSSC 1999
[3] Tang K. W. et al. CSICS [4] Huang P. et al, ISSCC 2006

18. Conclusions
Demonstrated a design methodology for low phase noise in W-Band VCOs
Biasing at JpeakfT minimizes phase noise in W-band VCOs
Performed a direct comparison of identical VCOs fabricated in different technologies
LC-oscillator frequency is insensitive to technology scaling
Higher fT technology yielded VCO with lower phase noise
Higher fMAX technology yielded VCO with improved output power
Future work is required to fully support these conclusions
Noise figure measurements in the W-Band (correlate to Y-parameter method)
Verify JNFmin in the W-Band and support biasing near JpeakfT for min. phase noise

19. Technology Overview – fT/fMAX Scaling
Improvement in peak fT/fMAX has two contributions
Layout  stripe contact, decreased emitter width 0.17mm to 0.13m
Vertical profile and processing  doping, materials, epitaxy, etc.
How much of the speed improvement is due to each contribution?
Measure the 0.13mm HBT layouts fabricated in the 0.17mm process
Scaling the emitter width alone doesn’t change current density for peak fT, but does improve speed.