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Senior Capstone Project: Fast Tuning Synthesizer Member: Nathan Roth Advisors: Dr. Huggins Dr. Shastry Mr. James Jensen Date:December 9, 2003.

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Presentation on theme: "Senior Capstone Project: Fast Tuning Synthesizer Member: Nathan Roth Advisors: Dr. Huggins Dr. Shastry Mr. James Jensen Date:December 9, 2003."— Presentation transcript:

1 Senior Capstone Project: Fast Tuning Synthesizer Member: Nathan Roth Advisors: Dr. Huggins Dr. Shastry Mr. James Jensen Date:December 9, 2003

2 Presentation Outline Project Summary Standards and Patents Functional Description Detailed Description Preliminary Laboratory Work/Results Preliminary Bill of Materials Preliminary Spring Semester Schedule

3 Project Summary Creation of a frequency synthesizer –Use of direct synthesis approach Design of synthesizer using indirect synthesis –Use of phase-locked loops

4 Project Summary Desired Characteristics –Output Frequency Range of 3.4 GHz to 4.6 GHz –Step Size of 50 MHz –Output Power of 0 dBm, ± 3 dB –Output Spurs < -45 dBc –Tuning Time < 500 ns, 200 ns if possible –Use of an External 100 MHz Reference Signal

5 Project Summary Actual Characteristics –Output Frequencies of 3650, 3700, 3850, 3900, 4450, 4500, 4650, and 4700 MHz –Output Power of 0 dBm, ± 3 dB –Output Spurs < -45 dBc –Tuning Time < 500 ns, 200 ns if possible –Use of an External 100 MHz Reference Signal

6 Standards –Depends Upon Application –C, X, and KU Band Channels: MIL-STD –Military Satellite Communications (MILSATCOM): MIL-STD : Interface Standard MIL-STD : Message Format MIL-STD : Interface for Satellite Multiplexers and Demultiplexers

7 Patents Patent Number 5,166,629 Grant Watkins and John Muhlbair of Westinghouse Electric Corporation on November 24, 1992

8 Functional Description Fast Tuning Frequency Synthesizer 3.6 – 4.6 GHz 100 MHz Reference D2 D1 D0 Digital Input Command Desired Output Frequency

9 Detailed Description

10 Input Module

11 Resolution Modules

12 Basis Frequency Modules

13 Switch Selection Module

14 Output Module

15 Preliminary Laboratory Work Design and Simulation of Ideal Chebyshev Filters Currently Adding Parasitic Effects –Real Component Values –Real Inductor Responses –Microstrip Transmission Effects –Via Connections

16 Preliminary Laboratory Work Filter Design –Insertion Loss Method

17 Preliminary Laboratory Work Filter Design

18 Preliminary Laboratory Work

19 Ideal S11 = Dark Blue Ideal S21 = Aqua Blue Actual S11 = Red Actual S21 = Purple

20 Preliminary Laboratory Work

21

22 Preliminary Bill of Materials Part NumberMakerDescriptionQtyPriceTotal Price HMC435MS8GHittiteSPDT, Hi Isolation, DC- 4 GHz PE3512PeregrineDivide By 4, DC MAX2671Maxim IC400 MHz To 2.5 GHz Upconverter Mixers SYK-2RMini-CircuitsFrequency Doublers, MHz HMC188MS8HittitePassive Frequency Doubler, GHz Input HMC187MS8HittitePassive Frequency Doubler, GHz 12.35

23 Preliminary Bill of Materials MSA-2743AgilentCascadable Silicon Bipolar Gain Block MMIC Amplifier ABA-53563Agilent3.5 GHz Broadband Silicon RFIC Amplifier HMC315HittiteGaAs InGaP HBT MMIC Darlington Amplifier, DC GHz AG604-89WJIngap HBT Gain Block TK10-KIT-NDToko250 Pcs - 10 Ea Of 25 Values SubstrateRogers Corporation RO4003,.020 Mil Thick, 1.4 Mil Foil Total172.53

24 Preliminary Spring Semester Schedule WeekTask Winter BreakResearch and understand phase locked loop (PLL) theory and circuitry Begin design of PLL system Finalize filter design and simulations Begin implementing as parts arrive Full scale simulation of direct synthesis (DS) system Jan 19 – 25Design of PLL system DS system simulation Jan 26 – Feb 1Design PLL system DS system simulation Have all filters tested and built Feb 2 – 8Complete design of PLL system DS system simulation Feb 9 – 15Simulation of PLL system Complete DS system Simulation

25 Preliminary Spring Semester Schedule Feb 9 – 15Simulation of PLL system Complete DS system Simulation Feb 16 – 22Simulation of PLL system Feb 23 – 29Complete simulation of PLL system March 1 – 7Components Arrive, Begin Soldering, Testing, and Biasing Components March 8 – 14Physical implementation of DS March 15 – 21Physical implementation of DS, Spring Break? March 22 – 28Begin DS full scale testing March 29 – April 4DS full scale testing April 5 – 11Complete DS full scale testing April 12 – 18 April 19 – 25Student Expo April 26 – May 2Present successful findings

26 Fast Tuning Synthesizer Any questions?


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