Presentation on theme: "Design of an LC-VCO with One Octave Tuning Range"— Presentation transcript:
1Design of an LC-VCO with One Octave Tuning Range Andreas Kämpe and Håkan OlssonRadio Electronics-LECS/IMITRoyal Institute of Technology (KTH)
2IntroductionVCO research has largely focused on reducing phase noise, not tuning range.Multi standard transceivers requires wideband VCOs with low phase noiseGoal: Designing a VCO with one octave tuning range while maintaining a low phase noise and low power consumption.
3VCO topologies LC tank Delay element + Low phase-noise. + Low power consumptionLarge chip areaTuning range (limited by CMAX/CMIN).Delay elementRing, transmission line, and relaxation oscillators+ Small chip area- High phase noise and realativly high power consumption.
4VCO Architecture Complementary structure (N & P) MOS => larger amplitude and symetric rise/fall time =>Reduced power / phase noise
5LC-tank and wide tuning range One octave tuning range =>Requires a Capacitance tuning of 2 octaves.Tuning capacitor Cmax / Cmin > (paracitcs: CP)Low voltage and large Cmax/Cmin => High varactor sensitivity (VCO gain) => sensitive to noise on the control line.
6Discrete tuning Bandswitching CMOS technology offers excellent switches.BandswitchingThe switched capacitors are used as band selectors (coarse tuning)Channel selection is performed digitally.+ Increased tuning range+ Reduces the varactor gain => phase noise reduction.
7Switch limitations (MOSFET) Low capacitive load Large tuning rangeMinimum loss Low power consumption
8Loss or capacitive load. Trade-offLoss or capacitive load.Minimum loss = reduce Rds-on = wide transistor with minimum gate length.Minimum capacitive load = reduce Cgs /Cgd = narrow transistor with minimum gate length.
9NMOS transistors (higher transconductance). Switch OptimisationNMOS transistors (higher transconductance).Drain / source are AC coupled (band sw cap) and biased via resistors => maximizes (Vgs-Vt)=> Reduced Rds-on
13Varactor Less steep voltage to capacitance transfer. Accumulation-mode mos varactors =>Less steep voltage to capacitance transfer.4 varactors are conected anti parallell =>Differential operation and control =>Common mode rejection
14Inductor + Differential inductor (increased coupling). + 3 metal layers (M6, M5, M4) are stacked on top of each other => reduces the series resistance. => increased Q- Increased capacitive load (Lower metal layers are closer to the substrate).
15Inductor simulationsOptimized and designed with ASITIC and ADS.
16Inductor modelLumped model of a transmission line.
17Inductor-model simulations Lumped model error ”Real(S)”.
18Inductor-model simulations Lumped model error ”Imag(S)”.
19Amplitude Variations Requires an adjustable negative resistance => The oscillation amplitude varies considerably across the wide tuning rangeRequires an adjustable negative resistance =>Achieved by controlling the biasing current.
20VCOThe band selection also controlles the biasing current. => Constant oscillation amplitude over the entire tuning range.
22VCO’sVCOTech[um]Tuning range[%]FOM[dBc/Hz]“A 5.9 GHz Voltage-Controlled Ring Oscillator in 0.18 μm CMOS”, IEEE J. Solid-State Circuits 39, pp , Jan 2004.0.2518-183“A 1.8 GHz higly-tunable low phase-noise CMOS VCO”. Custom Integrated Circuits Conference, CICC. Proceedings of the IEEE 2000, pp May 2000.28”New wideband/dualband CMOS LC voltage-controlled oscillator”. Circuits, Devices and Systems, VOl 150. Proceedings of the IEEE 2003, pp Oct 2003.98-158.3*“A 15-mW Fully Integrated I/Q Synthesizer for Bluetooth in 0.18 μm CMOS”, IEEE J. Solid-State Circuits 38, pp , July 2003.0.1816-174.5*“Design of Wide-Band CMOS VCO for Multiband Wireless LAN Applications”, IEEE J. Solid-State Circuits 38, pp , August 2003.0.13 SOI58.7-186.6This74-190* Quadrature VCO
23ConclusionsIt is possible for a VCO to have a large tuning range combined with a low phase noise and low power consumption. This design has a very good performance expressed in FOM (-190 dBc/Hz/mW) and superior if the wide tuning range is taken in account.Large chip Area, due to many capacitors and a large inductor. If the oscillator was designed to be operated at a higer frequency, the Chip area could be decreced (smaller LC tank) The down side is an increaced loss in the switches (capacitor array).