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Silicon Strip R&D Activity in Korea Introduction Sensor design and simulation Pre-results of 1 st mask performance Status of 2 nd mask design Summary B.G.

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Presentation on theme: "Silicon Strip R&D Activity in Korea Introduction Sensor design and simulation Pre-results of 1 st mask performance Status of 2 nd mask design Summary B.G."— Presentation transcript:

1 Silicon Strip R&D Activity in Korea Introduction Sensor design and simulation Pre-results of 1 st mask performance Status of 2 nd mask design Summary B.G. Cheon (Chonnam Natl Univ.) On behalf of Korean Silicon Working Group

2 Generic silicon sensor R&D since 2001 Silicon charge detector for CREAM balloon experiment Started working on silicon sensor R&D for Belle upgrade Looking for any application to other fields 7 institutions so far … Korean silicon working group Kyungpook National University Ewha Womens University Seoul National University Korea University Yonsei University Sungkyunkwan University Chonnam National University

3 Global design layout/parameter concepts can be referred to other presentations in this workshop. Silicon tracker R&D for ILC Intermediate tracker - tracking efficiency - linking efficiency - matching efficiency - standalone tracker main tracker - momentum resolution - tracking efficiency

4 Double-sided silicon strip sensor type Three metal process Implanted strips in ohmic side are orthogonal to the strips in juction side Readout strips in junction side are parallel to the strips of ohmic side DSSD sensor design Metal 1 and metal 2 contact (VIA) n+ ohmic side p+ junction side 1 st metal 2 nd metal readout line n+ ohmic components: # : implanted n+ # : p-stop # : SiO 2 # : Al for readout p+ junction components: # : implanted p+ # : 1 st metal # : SiO 2 # : VIA # : 2 nd metal

5 Simulation package : Silvaco TCAD ATHENA – process simulation ATLAS – device simulation PIN diode simulation calibrates DSSD simulation Structure & mesh Implantation (Boron, Phosphorus) Electric potential & field IV & CV characteristics Response of injected photon into the DSSD DSSD sensor simulation

6 Structure N-type Si(100), 8.5k, 380 m

7 Implantation Annealing 900 o C, N 2, 90min at P+ Annealing 900 o C, N 2, 140min at N+ N strip = PhosphorusP strip = BoronP stop = Boron

8 IV & CV Leakage current (I-V)C-V1/C 2 -V

9 Photon injection into DSSD photon : wavelength = 0.6 m, intensity=100W/cm 2 0V Total current densitye current densityh + current density 150V

10 Wafer layout (1 st mask) Mask design package : Cadence (Solaris)

11 DSSD sensor parameters List DC – Type unit p+ siden+ side Sensor size55610 x (sawing line included)μm 2 Wafer thickness380μm Strip pitch interval10050μm Readout pitch interval50 μm # of implanted strips512 # of readout strips512 Strip pitch length μm Strip pitch width99μm Readout pitch width99 μm

12 Test clean room

13 Sensor profiles n+ implanted n+ side p-stop in atollVIA in hourglassreadout pad in staggering guard ring p+ implantedreadout strip p+ side

14 P-side measurement Probe n bulk pad(ground) on n-side & p-guard ring ( ) on p-side

15 Total leakage current/sensor These are disappeared after insulating wafer edges

16 Total capacitance/sensor

17 Specification of 2 nd mask design N-sideP-side Sensors 512ch 50 m pitch512ch 100 m pitch 2types Test PatternsMiniature 16ch 50 m pitch 32ch 50 m pitch 64ch 50 m pitch 16ch 100 m pitch 32ch 100 m pitch 64ch 100 m pitch Pixel Arrayn+ implantation 25 m 5 5 array 50 m 5 5 array 100 m 5 5 array PIN Dioden+ implantation 1cm 1cm diode SSD R&D (Single Strip Detector) n+ implantation 100 m pitch 2 types SDD R&D (Silicon Drift Detector) 25 m sensor 25 m sensor surrounded by p+ imp. p+ implantation Multi-purpose mask: sensors + various test patterns

18 N-side 512ch 50 m pitch 1x1cm 2 PIN diode 64ch 50 m pitch 16ch 50 m pitch Rear-side of SSD Pixel Array For SDD R&D 32ch 50 m pitch

19 P-side 512ch 100 m pitch w/o hourglass (sensor-1) 512ch 100 m pitch w/ hourglass (sensor-2) 1cm PIN diode For SDD R&D Pixel array 16ch 100 m pitch 16ch 100 m pitch SSD 32ch 100 m pitch 64ch 100 m pitch

20 P-side (sensor-1) Implant w/ hourglass perpendicular to metal designed to reduce capacitance not applied to VIA region 512ch 100 m pitch sensor

21 Test pattern: Miniature S/N measurement of each pitch strip sensor after making wire bonding complete. Three types of sensors have been prepared. 16/32/64 channels P-side :16ch 100 m pitch Sensor N-side :16ch 50 m pitch sensor Case of wire bonding

22 Test pattern: P-side SSD Metal size is larger than p+ implant by reducing contact size. Metal size is smaller than p+ implant by keeping contact size. SiO 2 p+ contact1 st Metal SiO 2 VIA 2 nd Metal P-side: two metal processes It is needed to make it compatible with other p+ implantation. 16ch 100 m pitch sensor(55610 x 5560) p+ implantation Metal p+ implantation

23 Test pattern: pixel array Case of wire bonding in each diode Case of readout pad in each diode Pixel size : 25 25, 50 50, ( m 2 ) Each sensor array : 5 5 matrix Readout pad option was added to make wire bonding easy during the measurement of S/N

24 Test pattern: SDD 50 m n+ implant 100 m 100 m metal R&D pattern for Silicon Drift Detector Sensor size : 1cm 1cm (guard ring included) N-side : n+(sensor) & p+ implant except the sensor P-side : p+ implant in total

25 Summary DSSD sensors fab-out (~20 wafers, 3 sensors/wafer) and IV & CV have been measured. automatic probe station & wirebonder purchased and installed faster and more reliable measurement 2 nd mask design including various test patterns is almost ready. Fabrication and measurement will be done within two months. Silicon Drift Detector R&D has just been started. Irradiation test for checking sensor rad-hardness is being planned. Readout & DAQ design and production are in progress.

26 Backup sildes

27 CREAM(Cosmic Ray Energetics And Mass) balloon exp. To measure energy spectrum of each elements in ~10 15 eV First mission of design, fab. and integration performed in Korea Sensor size=1.1cm 2 ; S/N>4 ; Total 1000 channels CREAM Silicon Charge Detector

28 Electric potential Reverse bias ( 0V ~ -90V )

29 Electric field P_strip region (P+) N wafer region P_strips doping concentration is higher than N wafers. So N_bulk regions electric field is spread out widely, but the slope of P_strip regions field is very steep. In depletion region, electric field is not zero.

30 Electron concentration The higher reverse bias is, the larger depletion region is

31 Recombination rate The higher reverse bias is, the larger depletion region is

32 N-side sensor 512ch 50 m pitch sensor p-stop guard ring pad

33 P-side (sensor-2) Implant w/o hourglass hard to implement hourglass in the mask process compare btw w/ and w/o hourglass 512ch 100 m pitch sensor

34 SENS technology

35

36 Test pattern: SDD type-1 Silicon Drift Detector R&D pattern guard ring : 1cm 1cm N-side. 50 m n+ implant 100 m 100 m metal

37 Implantation Annealing 900 o C, N 2, 90min at P+ Annealing 900 o C, N 2, 140min at N+ N strip = Phosphorus P stop = Boron P strip = Boron


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