Assembly unit : Brick Electomagnetic (14) Hadronic (14) Skin Design: JINR(Dubna)/FNAL/BNL W plates: US Mechanics: JINR(Dubna) Assembly: BNL Minimal brick size is 2 x 4 sensors Maximal brick size is 2 x 7 sensors ROUs not shown
Layer geometry Hadronic segment (6 sampling layers per brick): 2x5- 4 2x7- 10 EM segments (14 sampling layers per brick): 2x4- 4 2x6- 6 2x7- 4
Readout units in a single NCC detector 2x4 -> 56 2x5 -> 24 2x6 -> 84 2x7 -> 116 Total Pad-Sensors in a Single NCC unit 3320 Total wafers for Pad Sensors (75% Yield) 4427
Assembled Read-out-Unit (sampling layer) W Carrier board Sensor assembly Output connectors Ground wire (bond) Si Sensor 2x112 analog lines maximum
NCC EM-Brick (from Proposal) W Stripixels pads Cu ski n Skins are held by flat-headed screws threaded into W
Comments from FNAL (SiDet) Introduce ground layer separating strip lines from sensors; Connect all ground layers inside carrier board using multiple vias (at least 5 per sensor); Insure continues ground connection between carrier board and absorber plate (gold plate edges). Comments from Instrumentation (BNL) Make sure detector ground is separated from PHENIX ground; Introduce Faradey cage (box insulated from PHENIX ground) around preamp boards. Make it extension of the bricks Cu-skin. Connect it to the preamp ground. Use shielded cables. Shield could be connected to detector grounds on both ends.
NCC Bricks (most recent) W Stripixels padsCu skin Plate edges are Au-plated Skins are held by flat-headed screws threaded into W Total depth 19.5 cm W thickness is 4 mm everywhere Pb thickness TBD to fully occupy 19.5 depth limit Signal summation over 7 layers in EM and 6 layers in Had segments Pb
Soldering interconnects to carrier boards (based upon earlier idea from Ekaterinbourg) Interconnect Spacer Bump-bonds Si W Carrier
Proposed material for interconnect and spacer boards is Bismaleimide triazine BT-material BT-prepreg BT-epoxy Material data sheets could be found for example at ISOLA web page http://www.isola- usa.com/en/products/
Sensor interconnect board Wire-bonding via Wire-bonding pad Trace Bump bonding pad Bump-bonding pad cluster
Top ground layer of the carrier board (single sensor area) Cu plating Wire-bonding area Bump bonding pad Signal via Ground via Everything yellow are openings in the top ground layer
Readout unit in minimal configuration - use single signal layer for sensors 0-3, second layer for sensors 4 to 6; - position lines from 4 pads along the long board axis together in connector; - line from via always goes first towards top of the board – this will make pin mapping in the top and bottom connectors identical: To make this mapping clean it is probably worth grouping pins in blocks of 28 (maximum number of contacts along single horizontal line on 2x7 ROU. There will be 4 blocks altogether with 16 pins used in each block in the minimal configuration. Proposed pad-to-pin mapping is on the next page. 3 2 1 0 1010 0-0 3-3 3-0 0 120 0 0-3
Connectors, cables and pad-to-pin mapping Connectors: 120 pins HIROSE-FX11L with ground plate (additional 12 ground pads connected to ground plate); Cable: flexible polyimid, needs layout, prototyping and testing (S.Booze); Mapping –Ground layers interconnected by vias are connected to all 12 ground pads; –Last 8 pins in the connector are unused; –Pins corresponding to missing sensor positions on boards shorter then 7 sensors will stay unused. –Proposed signal-to-pin mapping for both signal layers (single row of sensors) is in the two tables below. sensor3-02-00-03-00-0 pad0-31-32-33-30-3…3-30-2...3-2…3-0 pin1213141516274055111 Top signal layer (sensors 0 to 3 counting from connector) sensor6-05-04-06-04-0 pad0-31-32-33-30-3…3-30-2...3-2…3-0 pin0123411283995 Bottom signal layer (sensors 4 to 7 counting from connector)
Assembly sequence production of W plates; production of a similar size carrier pc boards (1.2 mm thick, 5 layers, Cu on both outside surfaces). pc-boards are sent out for bump installation (initially only 50% of bumps in a cluster are installed). We will need to decide if bumps are installed before or after W plate and pc - board are laminated together; W plate and pc board are glued together. We will have couple of positioning pins, then (probably) two beads of silver epoxy along the whole length of W plate with the rest of the plate covered with prepreg or BT-epoxy or whatever experts recommend; production of interconnect boards (0.15 mm) whith 3mm vias for wire bonding with traces leading to clusters of bump-bonding pads. BT-material; production of spacer boards: no Cu, just holes to accomodate wire bonding (diameter ~6 mm) and bonding bumps (depending on the number of bumps in a cluster). BT-material; laminating those two boards together (BT-prepreg). Resulting laminate must be rather stiff and flat; gluing sensor to laminate (either known glue or BT-epoxy or BT-prepreg, we need to test or rely on expertize); wire bonding sensors through the vias (edge bonding); encapsulating wire-bonds; bump bonding sensor assemblies to W-pc laminate. This last operation is very, very delicate. We will have up to 14 fully tested sensor assemblies and everything depends on success of this operation. Quite a challenge.
Plans (next three to six months) Continue the discussion of the pad-structured sampling layer design with experts in manufacturing (Helsinki, Dubna, RIKEN, Ekaterinbourg); Design and prototype flexible cables; Do the board layout (does not really depends on the choice of assembly approach; Prototype all boards and test elements of the assembly approach; Get and test first generic W plate (ordered); Finish mechanical design (looking for engineering help); Start ordering components for prototype construction. It is uncertain if well be doing it at BNL, we may not have the right kind of environment. We need either one more full-time detector physicist with right kind of expertise or commitment from one of participating labs.