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PEM Qualification Requirements

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Presentation on theme: "PEM Qualification Requirements"— Presentation transcript:

1 PEM Qualification Requirements
For Radiation Hardened Non-Hermetic Products Qualifiable for Space Flight Applications

2 Plastic vs Hermetic Moisture Effects Weight Differences
Shock & Vibration Outgassing Effects Package Qualifications Board Qualifications Assembly Roadmap

3 Moisture Effects All Xilinx PEMs are certified according to method JESD20 as Level 3 or better JESD20 certification includes three passes of solder simulation to allow for rework “POPCORN” is a myth after successful board assembly Space is actually a benign, dry environment for PEMs.

4 “POPCORN” “POPCORN” can only occur during the assembly process if industry standard rules are not followed “POPCORN” is caused by liberation of the steam formed during the rapid thermal excursions to 230°C seen in the solder reflow process “POPCORN” can only occur when adsorbed moisture is turned to steam faster than it can escape “POPCORN” does not occur in operation because temperatures and temperature ramp rates in operation are simply not high enough

5 Thermal Comparison theta Ja
PLCC °C/watt PQ °C/watt BGA °C/watt BGA °C/watt FG °C/watt FG °C/watt FG °C/watt PG °C/watt PG °C/watt CB °C/watt CG °C/watt no higher pin count ceramic packages are currently available from Xilinx

6 Weight Comparisons PLCC84 6.8gr PQ240 7.1gr BGA432 7.1gr BGA560 12.3gr
FG gr FG gr FG gr PG gr PG gr CB gr CG gr no higher pin count ceramic packages are currently available from Xilinx

7 Launch Cost Comparison based on $10,000/lb to GEO
CG560 $969.00 BG560 $270.00 FG900 $ 92.00

8 Shock & Vibration The lower weight (mass) of PEMs gives them a distinct advantage in passing board mount vibration tests PEMs are solid encapsulation, so ultrasonic cleaning and shock cannot affect bond wire integrity PEMs are qualified to all the shock, vibration and life tests utilizing the following standard test methods: method T/C condition C method T/S condition C method Steady State Life method Lead Integrity method Vibration

9 Shock & Vibration (continued)
PEMs offer the additional advantages of being manufactured on main stream, high volume commercial manufacturing lines with: method 2011 bond strength, under SPC control with CpKs > 2.0, on QML certified lines method 2019 die shear, under SPC control with CpKs > 2.0, on QML certified lines method 2012 radiography, with die attach coverage and bond sweep under SPC control, on QML certified lines

10 Outgassing Effects Data Source: NASA Web Sites Key Parameters
TML (total material loss) CVCM (condensable volatiles recovered) NASA Specifications A TML < 1.0% CVCM < 0.1% B TML < 3.0% CVCM < 1.0% X TML > 3.0% CVCM > 1.0%

11 Packaging Materials Injection Molded Packages Ball Grid Packages
PLCC: Nitto MP 8000 PQFP: Nitto MP8000, Sumitomo 7304 PDIP/SO: Sumitomo 6300 Ball Grid Packages SBGA: Hysol FP4450, BT Laminate BGA: Plaskon SMBT-1, BT Laminate

12 Outgas Data Injection Molded Packages
PQFP, PDIP, SO, BGA Sumitomo 6300 (PDIP, SO, PLCC) TML 0.27% CVCM 0.00% Sumitomo 7304 (PQFP, TQ/VQ) TML 0.17% Nitto 8100 (PQFP, PLCC) TML 0.20% CVCM 0.01% BT Laminate (BGA substrate) TML 0.78% Plaskon SMTB-1 (BGA mold compound) TML 0.28%

13 Outgas Data Encapsulated Packages
SBGA BT Laminate (SBGA substrate) TML 0.78% CVCM 0.01% Hysol FP4450 (SBGA encapsulate) TML 0.13% CVCM 0.00%

14 Circuit Board Outgas for comparison
FR-4 (various formulations) TML % (range) CVCM % (range) Polyimide Laminate TML 0.78% CVCM 0.01% Conclusion: The PC board materials have considerably more outgassing potential than the various materials used to fabricate PEMs.

15 Possible Indicators of Quality Manufacturing
ISO9000 Conformance DSCC QML Certification PURE Approval Open Data Communications Reliability Monitoring Programs SPC Data Availability Applications Support SPC Control Programs TL9000 Certification Subcontractor Control Programs PCN Process Mask Revision Control Hardness Assurance Data SEU Upset Data

16 Typical Wafer Fab SPC Report

17 Parametric SPC Report

18 Metal Step Coverage of CMP Process

19 Metal Step Coverage of Reflow Process

20 Bond Integrity and Sweep

21 Bond Pull Data on Completed Assemblies
One device was pulled for wire bond pull test. Minimum = 8.3 Maximum = 13.6 Average = 10.1 Std. Dev. = 1.2 MODE : 1 = Break at Neck

22 Plastic Qualification Tests
Temperature Cycling (T/C) Moisture Resistance (PCT) Humidity Temperature Bias (85/85) Highly Accelerated Stress Test (HAST)

23 Temperature Cycling (T/C)
Performed to 883 Method 1010 Moisture Pre-stress to Level 3 Full Solder Simulation per JESD20 Condition C (-65°C/+150°C) for Injection Molded Packages (PQFP) Condition B for Ball Grid Packages Full Production Testing at end of Stress Package Decapsulation at End of Test to check for Die Cracking

24 Results of Temp Cycle Testing

25 Pressure Pot Testing Performed in 121°C Steam at 2 atm
Moisture Pre-stress to Level 3 Full Solder Simulation per JESD20 Minimum of 96 Hours Full Production Testing at end of Stress Package Decapsulation at End of Test to Examine for Corrosion

26 Moisture Resistance Testing

27 Temperature Humidity Bias
Performed to 85°C, 85%RH, Nominal Vcc Moisture Pre-stress to Level 3 Full Solder Simulation per JESD20 Minimum of 1,000 hours Full Production Testing at end of Stress Package Decapsulation at End of Test to check for Corrosion

28 Temperature Humidity Bias

29 Highly Accelerated Stress Test
Performed at 130°C, 85%RH, 2atm, Vcc Moisture Pre-stress to Level 3 Full Solder Simulation per JESD20 Minimum of 100 hours Full Production Testing at end of Stress Package Decapsulation at End of Test to check for Corrosion

30 Highly Accelerated Stress Test

31 Board Level Reliability Test FG676, FG680, FG860, & FG1156

32

33 Summary of Test Results
Package Test Condition Cycles Completed # Tested # Failed 1st Failure (cycles) Mean Life FG676 TC1 2112 32 27 1341 1830 TC2 2126 26 1434 1788 TC3 7029 4 5909* N/A FG680 5222 29 20 4219 4796 3960 16 2883 3891 6790 FG860 5044 FG1156 3108 30 1601 2386 2507 48 1666 2256 * First failure t All Packages Passed at least 1000 cycles of TC1 & TC2 Conditions t TC2 is more Damaging than TC1 for FG680 (Heat Slug Package), No Significant Difference for FG676 & FG1156 (PBGA Type Packages)

34 2nd Level Reliability Test - FG676 (PBGA)
Package Package Size I/O Pitch Ball Size Pad Opening Type Die Size Substrate FG676 (PBGA) 27x27 676 1.0 0.6 0.48 SMD 17.8x17.8x0.3 0.56 Thk, 4 Layer All Dimensions in mm Package Test Condition Cycles Completed # Tested # Failed 1st Failure (cycles) Mean Life FG676 TC1 2112 32 27 1341 1830 TC2 2126 26 1434 1788 TC3 7029 4 5909* N/A t Motherboard 1.6mm Thick 0.38mm Pad NSMD t Test Data 1.0 5.0 10.0 50.0 99.0 500.0 5000.0 FG676 Cycles to Failure Cumulative % Failed Weibull TC1 b1=9.3, h1=1896.5, r=1.0 TC2 b2=12.6, h2=1852.2, r=1.0 Failures Primarily Around Die Edge No Significant Difference Between TC1 and TC2 Results

35 2nd Level Reliability Test - FG680 (SBGA)
Package Package Size I/O Pitch Ball Size Pad Opening Type Die Size Substrate FG680 (SBGA) 40x40 680 1.0 0.6 0.48 SMD 20.3x20.3x0.3 0.98 Thk, 3 Layer All Dimensions in mm Package Test Condition Cycles Completed # Tested # Failed 1st Failure (cycles) Mean Life FG680 TC1 5222 29** 20 4219 4796 TC2 3960 32 16 2883 3891 TC3 6790 N/A t Motherboard 1.6mm Thick 0.38mm Pad NSMD t Test Data 1.0 5.0 10.0 50.0 99.0 1000.0 FG680 Cycles to Failure Cumulative % Failed Weibull TC1 b1=22.6, h1=4913.2, r=1.0 TC2 b2=9.9, h2=4092.2, r=1.0 TC2 is 1.25X More Damaging

36 2nd Level Reliability Test - FG1156 (PBGA)
Package Package Size I/O Pitch Ball Size Pad Opening Type Die Size Substrate FG1156 (PBGA) 35x35 1156 1.0 0.6 0.48 SMD 23.11x21.13x0.3 0.56 Thk, 4 Layer All Dimensions in mm Package Test Condition Cycles Completed # Tested # Failed 1st Failure (cycles) Mean Life FG1156 TC1 3108 32 30 1601 2386 TC2 2507 48 1666 2256 TC3 5044 N/A t Motherboard 1.6mm Thick 0.38mm Pad NSMD t Test Data 1.0 5.0 10.0 50.0 99.0 1000.0 FG1156 Cycles to Failure Cumulative % Failed Weibull TC1 -Die Region b1=8.9, h1=2521.7, r=1.0 -Perimeter b2=4.3, h2=4268.4, r=0.9 TC2 b3=19.4, h3=2319.6, r=0.9 2 Separate Nets/Device t Inside the Die t Outside the Die Nets Inside the Die Failed First t Failures Primarily Underneath the Die No Significant Difference Between TC1 and TC2 Results

37

38 Packaging Industry Evolution
XILINX High Performance High Pincounts / I/Os Product Miniaturization Portables CSP mm FBGA 1.0 mm BGA 1.27mm AREA ARRAY SMT Packages 1991  Millennium PLCC 1.27 mm PQFP mm SOIC mm Size and Performance Limitations PERIMETER SMT Packages DIPs 2.54 mm Pitch THRU-HOLE Packages 1960’s

39 Advanced Package and Technology Roadmap Y1997-Y2002
10 20 30 40 Power (Watts) 42.5 x 42.5 45 x 45 Package Size Wirebond Flip Chip Pincount Range 19 x 21 23 x 21 24 x 22 28 x 25 Max Die Size

40 Xilinx BGA Packaging Strategy
Virtex Spartan CPLD mm mm “SBGA” Cu-Based BGA pins High Power / Thermal Dissipation High Density / IOs High Performance / Frequency Design Feature Crammed, High Speed Switching Systems Flip Chip BGA > pins 1.38 mm “FinePitch BGA” Plastic Molded BGA pins “CSP” Flex-Based BGA pins 1.0mm Highest Power / Thermal Dissipation Highest Density / IOs High Performance Interconnect Enabler Feature Crammed, High Speed Switching Systems Advanced High-End Products Mid-Range / Mainstream General Functions Off-the-Shelf User Friendly Cost Effective Miniaturization, Light Weight Wireless Communication Height Restriction PCMCIA, Portables Low Cost and High Volume


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