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B5_Fabula 1 PEM Qualification Requirements For Radiation Hardened Non- Hermetic Products Qualifiable for Space Flight Applications.

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Presentation on theme: "B5_Fabula 1 PEM Qualification Requirements For Radiation Hardened Non- Hermetic Products Qualifiable for Space Flight Applications."— Presentation transcript:

1 B5_Fabula 1 PEM Qualification Requirements For Radiation Hardened Non- Hermetic Products Qualifiable for Space Flight Applications

2 B5_Fabula 2 Plastic vs Hermetic Moisture Effects Weight Differences Shock & Vibration Outgassing Effects Package Qualifications Board Qualifications Assembly Roadmap

3 B5_Fabula 3 Moisture Effects All Xilinx PEMs are certified according to method JESD20 as Level 3 or better JESD20 certification includes three passes of solder simulation to allow for rework POPCORN is a myth after successful board assembly Space is actually a benign, dry environment for PEMs.

4 B5_Fabula 4 POPCORN POPCORN can only occur during the assembly process if industry standard rules are not followed POPCORN is caused by liberation of the steam formed during the rapid thermal excursions to 230°C seen in the solder reflow process POPCORN can only occur when adsorbed moisture is turned to steam faster than it can escape POPCORN does not occur in operation because temperatures and temperature ramp rates in operation are simply not high enough

5 B5_Fabula 5 Thermal Comparison theta Ja PLCC °C/watt PQ °C/watt BGA °C/watt BGA °C/watt FG °C/watt FG °C/watt FG °C/watt PG °C/watt PG °C/watt CB °C/watt CG °C/watt no higher pin count ceramic packages are currently available from Xilinx

6 B5_Fabula 6 Weight Comparisons PLCC846.8gr PQ2407.1gr BGA4327.1gr BGA gr FG gr FG9004.2gr FG gr PG84 7.5gr PG gr CB gr CG gr no higher pin count ceramic packages are currently available from Xilinx

7 B5_Fabula 7 Launch Cost Comparison based on $10,000/lb to GEO CG560$ BG560$ FG900$ 92.00

8 B5_Fabula 8 Shock & Vibration The lower weight (mass) of PEMs gives them a distinct advantage in passing board mount vibration tests PEMs are solid encapsulation, so ultrasonic cleaning and shock cannot affect bond wire integrity PEMs are qualified to all the shock, vibration and life tests utilizing the following standard test methods: –method 1010 T/C condition C –method 1011 T/S condition C –method 1005 Steady State Life –method 2004 Lead Integrity –method 2005 Vibration

9 B5_Fabula 9 Shock & Vibration (continued) PEMs offer the additional advantages of being manufactured on main stream, high volume commercial manufacturing lines with: –method 2011 bond strength, under SPC control with CpKs > 2.0, on QML certified lines –method 2019 die shear, under SPC control with CpKs > 2.0, on QML certified lines –method 2012 radiography, with die attach coverage and bond sweep under SPC control, on QML certified lines

10 B5_Fabula 10 Outgassing Effects Data Source: NASA Web Sites Key Parameters –TML (total material loss) –CVCM (condensable volatiles recovered) NASA Specifications –ATML < 1.0%CVCM < 0.1% –BTML < 3.0%CVCM < 1.0% –XTML > 3.0%CVCM > 1.0%

11 B5_Fabula 11 Packaging Materials Injection Molded Packages –PLCC: Nitto MP 8000 –PQFP: Nitto MP8000, Sumitomo 7304 –PDIP/SO: Sumitomo 6300 Ball Grid Packages –SBGA: Hysol FP4450, BT Laminate –BGA: Plaskon SMBT-1, BT Laminate

12 B5_Fabula 12 Outgas Data Injection Molded Packages PQFP, PDIP, SO, BGA –Sumitomo 6300 (PDIP, SO, PLCC) TML 0.27% CVCM 0.00% –Sumitomo 7304 (PQFP, TQ/VQ) TML 0.17% CVCM 0.00% –Nitto 8100 (PQFP, PLCC) TML 0.20% CVCM 0.01% –BT Laminate (BGA substrate) TML 0.78% CVCM 0.01% –Plaskon SMTB-1 (BGA mold compound) TML 0.28% CVCM 0.00%

13 B5_Fabula 13 Outgas Data Encapsulated Packages SBGA –BT Laminate (SBGA substrate) TML 0.78% CVCM 0.01% –Hysol FP4450 (SBGA encapsulate) TML 0.13% CVCM 0.00%

14 B5_Fabula 14 Circuit Board Outgas for comparison FR-4 (various formulations) –TML % (range) –CVCM % (range) Polyimide Laminate –TML 0.78% –CVCM 0.01% Conclusion: The PC board materials have considerably more outgassing potential than the various materials used to fabricate PEMs.

15 B5_Fabula 15 Possible Indicators of Quality Manufacturing ISO9000 Conformance DSCC QML Certification PURE Approval Open Data Communications Reliability Monitoring Programs SPC Data Availability Applications Support SPC Control Programs TL9000 Certification Subcontractor Control Programs PCN Process Mask Revision Control Hardness Assurance Data SEU Upset Data

16 B5_Fabula 16 Typical Wafer Fab SPC Report

17 B5_Fabula 17 Parametric SPC Report

18 B5_Fabula 18 Metal Step Coverage of CMP Process

19 B5_Fabula 19 Metal Step Coverage of Reflow Process

20 B5_Fabula 20 Bond Integrity and Sweep

21 B5_Fabula 21 Bond Pull Data on Completed Assemblies u One device was pulled for wire bond pull test. Minimum = 8.3 Maximum = 13.6 Average = 10.1 Std. Dev. = 1.2 MODE : 1 = Break at Neck

22 B5_Fabula 22 Plastic Qualification Tests Temperature Cycling (T/C) Moisture Resistance (PCT) Humidity Temperature Bias (85/85) Highly Accelerated Stress Test (HAST)

23 B5_Fabula 23 Temperature Cycling (T/C) Performed to 883 Method 1010 Moisture Pre-stress to Level 3 Full Solder Simulation per JESD20 Condition C (-65°C/+150°C) for Injection Molded Packages (PQFP) Condition B for Ball Grid Packages Full Production Testing at end of Stress Package Decapsulation at End of Test to check for Die Cracking

24 B5_Fabula 24 Results of Temp Cycle Testing

25 B5_Fabula 25 Pressure Pot Testing Performed in 121°C Steam at 2 atm Moisture Pre-stress to Level 3 Full Solder Simulation per JESD20 Minimum of 96 Hours Full Production Testing at end of Stress Package Decapsulation at End of Test to Examine for Corrosion

26 B5_Fabula 26 Moisture Resistance Testing

27 B5_Fabula 27 Temperature Humidity Bias Performed to 85°C, 85%RH, Nominal Vcc Moisture Pre-stress to Level 3 Full Solder Simulation per JESD20 Minimum of 1,000 hours Full Production Testing at end of Stress Package Decapsulation at End of Test to check for Corrosion

28 B5_Fabula 28 Temperature Humidity Bias

29 B5_Fabula 29 Highly Accelerated Stress Test Performed at 130°C, 85%RH, 2atm, Vcc Moisture Pre-stress to Level 3 Full Solder Simulation per JESD20 Minimum of 100 hours Full Production Testing at end of Stress Package Decapsulation at End of Test to check for Corrosion

30 B5_Fabula 30 Highly Accelerated Stress Test

31 B5_Fabula 31 Board Level Reliability Test FG676, FG680, FG860, & FG1156

32 B5_Fabula 32

33 B5_Fabula 33 Summary of Test Results All Packages Passed at least 1000 cycles of TC1 & TC2 Conditions TC2 is more Damaging than TC1 for FG680 (Heat Slug Package), No Significant Difference for FG676 & FG1156 (PBGA Type Packages)

34 B5_Fabula 34 2nd Level Reliability Test - FG676 (PBGA) Package Motherboard –1.6mm Thick –0.38mm Pad NSMD Test Data –Failures Primarily Around Die Edge –No Significant Difference Between TC1 and TC2 Results PackageSizeI/OPitchBall Size Pad Opening Pad Type Die SizeSubstrate FG676 (PBGA)27x SMD17.8x17.8x Thk, 4 Layer All Dimensions in mm Package Test Condition Cycles Completed # Tested# Failed 1st Failure (cycles) Mean Life (cycles) FG676TC FG676TC FG676TC *N/A

35 B5_Fabula 35 2nd Level Reliability Test - FG680 (SBGA) Package Motherboard –1.6mm Thick –0.38mm Pad NSMD Test Data –TC2 is 1.25X More Damaging Package Test Condition Cycles Completed # Tested# Failed 1st Failure (cycles) Mean Life (cycles) FG680TC ** FG680TC FG680TC N/A PackageSizeI/OPitchBall Size Pad Opening Pad Type Die SizeSubstrate FG680 (SBGA)40x SMD20.3x20.3x Thk, 3 Layer All Dimensions in mm

36 B5_Fabula 36 2nd Level Reliability Test - FG1156 (PBGA) Package Motherboard –1.6mm Thick –0.38mm Pad NSMD Test Data –2 Separate Nets/Device Inside the Die Outside the Die –Nets Inside the Die Failed First Failures Primarily Underneath the Die –No Significant Difference Between TC1 and TC2 Results PackageSizeI/OPitchBall Size Pad Opening Pad Type Die SizeSubstrate FG1156 (PBGA)35x SMD23.11x21.13x Thk, 4 Layer All Dimensions in mm Package Test Condition Cycles Completed # Tested# Failed 1st Failure (cycles) Mean Life (cycles) FG1156TC FG1156TC FG1156TC N/A

37 B5_Fabula 37

38 B5_Fabula 38 Packaging Industry Evolution 1960s THRU-HOLE Packages DIPs 2.54 mm Pitch PQFP mm PLCC 1.27 mm PERIMETER SMT Packages SOIC mm High Performance High Pincounts / I/Os Product Miniaturization Portables Size and Performance Limitations 1991 Millennium BGA 1.27mm FBGA 1.0 mm CSP mm XILINX AREA ARRAY SMT Packages

39 B5_Fabula 39 Advanced Package and Technology Roadmap Y1997-Y Power (Watts) 42.5 x x 45 Package Size PincountRange 19 x x x x 25 Max Die Size

40 Xilinx BGA Packaging Strategy Highest Power / Thermal Dissipation Highest Density / IOs High Performance Interconnect Enabler Feature Crammed, High Speed Switching Systems Advanced High-End Products Mid-Range / Mainstream General Functions Off-the-Shelf User Friendly Cost Effective Miniaturization, Light Weight Wireless Communication Height Restriction PCMCIA, Portables Low Cost and High Volume Virtex Spartan CPLD mm mm SBGA Cu-Based BGA pins High Power / Thermal Dissipation High Density / IOs High Performance / Frequency Design Feature Crammed, High Speed Switching Systems Flip Chip BGA > pins 1.38 mm1.38 mm FinePitch BGA Plastic Molded BGA pins CSP Flex-Based BGA pins 1.0mm


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