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Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 1 Fermilab PAC Meeting April 12, 2001 Marcel Demarteau Fermilab Status and Scope DØ Run 2b.

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Presentation on theme: "Fermilab PAC Meeting, April 12-14, 2002 - M. Demarteau Slide 1 Fermilab PAC Meeting April 12, 2001 Marcel Demarteau Fermilab Status and Scope DØ Run 2b."— Presentation transcript:

1 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 1 Fermilab PAC Meeting April 12, 2001 Marcel Demarteau Fermilab Status and Scope DØ Run 2b Silicon Tracker Status and Scope DØ Run 2b Silicon Tracker For the Run 2b Silicon Group

2 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 2 Outline Brief reminder of design No change in overall layout of the detector Changes in sub-components »Advancement of design ] cooling layer 0 hybrids »Better performance ] details of stave design »Easier design ] Eliminated fingers on hybrid Schedule Completion May-June 05 Scope Picture based on Geant Model

3 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 3 Basic Layout Six layer silicon tracker, divided in two radial groups Inner layers: Layers 0 and 1 »Axial readout only »Mounted on integrated support »Assembled into one unit »Designed for V bias up to 700 V Outer layers: Layers 2-5 »Axial and stereo readout »Stave support structure »Designed for V bias up to 300 V Employ single sided silicon only, 3 sensor types 2-chip wide for Layer 0 3-chip wide for Layer 1 5-chip wide for Layers 2-5 No element supported from the beampipe Drilled Be Beampipe with ID of 0.96, 500 m wall thickness

4 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 4 Layer 0 Support Structure 12-fold crenellated geometry carbon fiber support possible use of pyrolitic graphite sensors cooled to T=-10 o C R in = 18.5 mm Silicon Analogue cable Hybrid Assembly 2-chip wide sensors 25 mm pitch, 50 mm readout Analogue cables for readout Hybrids off-board Staggered in z for 6 readouts per end per phi-sector Space is extremely tight ! Outside tracking volume

5 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 5 Layer 0 Support Structure Prototype support structure made by University of Washington Crenellated mandrel »Stacking sequences ] Cylindrical Shell: 3 ply 0º, 90º, 0º laminate ] Castellated Shell: 6 ply [0º, +20º, -20º] s laminate RTV pressure strips, vacuum bag Pressured to 85 psi Cured in autoclave at 275 °F castellated shell Measurements and comparisons of elastic properties of prepreg. laminates

6 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 6 Layer 1 Support Structure 12-fold crenellated geometry carbon fiber support Integrated cooling R in = 34.8 mm Assembly 3-chip wide sensors, 58 m pitch, axial readout Hybrids on-board 6-chip double-ended hybrid readout Cooling lines Silicon Hybrid Digital cable L0 Full view layer 1

7 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 7 Layers , 18, 24 and 30-fold geometry All layers: 5-chip wide sensors, 30 m pitch, 60 m readout Hybrids on-board 10-chip hybrid readout Stereo and axial readout Stereo angle obtained by rotating sensor Support Modules are assembled into staves Staves are positioned with carbon- fiber bulkheads Steady progress on stave design

8 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 8 Silicon Readout SVX4 Submitted (finally) to TSMC on March 28 SVX4 Test cards to qualify chip, design finished Analogue cable for Layer 0 Low mass, fine pitch cables to bring analogue signals outside of tracking volume Technically challenging »Trace width ~ 10 m, pitch 100 m »C ~ 0.4 pF/cm Two vendors »Dyconex (2 nd prototype) »Compunetics Hybrids Common technology with CDF First hybrids delivered Digital Cable (KSU) Two vendors: Honeywell, Basic Electronics Adapter Cards (KSU) Design nearing completion Digital cable

9 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 9 Progress Expect to have full scale prototype of all elements by this fall

10 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 10 Alternate Designs with Reduced Scope Given that many elements are already in prototype stage, reduced scope obtained by omitting various element No re-optimization considered Would set project back by at least 6-9 months Variation of radii, width of sensors different type of sensors … Options considered for reduced scope Omission of Layer 4 Omission of Layer 1 Omission of sensors at large |z| Folding in realism

11 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 11 Reference: TDR Design Fiber tracker has full coverage up to | | < ~1.6 Require silicon stand-alone tracking for | | > ~1.6 Studies based on full Geant simulation b-tag: signed impact parameter, E b > 20 GeV »Track selection within cone R < 0.5 of b-jet p T > 0.5 GeV/c, good 2, hits in silicon 2 »Impact parameter significance 2 tracks: d 0 / (d 0 ) > 3 3 tracks: d 0 / (d 0 ) > 2 Based on WH-events, with bs falling within acceptance

12 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 12 Omission of Layer 4 Consider CFT+SMT tracking One stereo measurement less Tracking efficiency and b-tagging eff. degraded But double number of tracks with poor quality (pattern recognition) 4 Si hits 5 Si hits 2 In addition lose 2% in lepton id.

13 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 13 Omission of Layer 4 Consider Silicon Stand-Alone tracking Important in forward region with no full coverage of CFT Important in lepton identification Important tool for consistency checks Tracking efficiency and fake rate Fake rate: factor 10 larger for tracks with 4/5 (TDR-L4) compared to 5/6 hits At same fake rate »Central region reduction of: track finding eff. by 10%, b-tag eff. by 20% »Forward region reduction of: track finding eff. by 22%, b-tag eff. by 40%

14 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 14 Omission of Layer 1 A priori undesirable Layer 1 also a contingency in case problems encountered with layer 0 »Deterioration of impact parameter resolution by ~10% for L2-L3 system Mistag rate doubles if layer 1 removed. Compare using same mistag rate

15 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 15 Folding in Realism So far assumed detectors are perfect; reality, however, is different Example: Run2a silicon detector »Barrels / F-disks / H-disks: 93%, 96%, 89% functioning devices Assume certain fraction of Si ladders dead, 30% inefficiency in CFT lyr 1 effect on b-tagging efficiency Fraction of non-working devices Relative increase in inefficiency

16 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 16 Reduced Coverage Remove sensors at large |z|, reduced | | acceptance Studied at generator level for WH events 23% decrease in acceptance for both b-quarks 8% decrease in acceptance for lepton from W-decay Overall loss in acceptance of 27%

17 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 17 Summary on Scope TDR design: b tagging efficiency of ~65% Higgs working group simulations assume even higher b-tag efficiencies Omission of any element would significantly affect physics reach and diverge from the basis of justification for Run 2b b-tagging efficiencies would fall below 50%, especially if analyses would require tighter tagging algorithm 20% loss in luminosity on 15 fb -1, 5 GeV reduction in reach on m H ( GeV) Assuming 12 fb -1 /3yrs

18 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 18 Summary Project is well into prototyping phase; significant progress has been made over the last 5 months Results from our studies indicate that all baseline elements are necessary to address physics opportunities of Run 2b Given the narrow window of opportunity, any reduction in scope would adversely affect the justification for Run 2b Project is well positioned to present Current full scale design Schedule Resource estimates Project cost estimate to the review committees to get this silicon detector baselined.

19 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 19 Outer Layer Modules Staves are assembled from readout modules Readout modules: 6 types »10-10 (axial, stereo) »10-20 (axial, stereo) »20-20 (axial, stereo) Stereo angle determined by mechanical constraints »10cm readout: = 2.5 o »20cm readout: = 1.25 o »For readout module, there will be a small gap at the transition Ganged sensors will have traces aligned Module configuration Layer 4-5 Layer

20 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 20 Stave Structure Stave is doublet structure of four readout modules Two layers of silicon »Axial and stereo »Two readout modules each separated by PEEK cooling lines Total of 168 staves Stave has carbon fiber cover Protect wirebonds Provide path for digital cables Staves are mounted in end carbon fiber bulkheads Cooling manifold similar to bulkhead design Layer 4-5 stave

21 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 21 Stave Readout Schematic Hybrid Digitizes Si analogue signal, launches the digital signal on the … Digital cable Flex circuit which brings signals to the … Junction card Passive element which transfers signals to high quality twisted pair signal cable which brings the signal to the … Adapter card Active element that provides the differential drive for the svx4 chip Hybrids Digital Cables Twisted Pair Cable Low Mass Jumper Cable Junction Card Layer 4-5

22 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 22 Hybrids Characteristics: Layer 0 »2-chip hybrids; each hybrid reads out one sensor Layers 1-5 »Hybrids are double-ended ] 6-chip hybrids for layer 1 ] 10-chip hybrids for layers 2-5 Design of Layer 1 hybrid complete »Ceramic hybrid (BeO) »6 layers »Connector pinout frozen Hybrids carry the bias voltage for layers 2-5 (300 V) One HV feed / hybrid; HV is split between up to 4 sensors Prototype hybrids for Layer 1 ready to be ordered 6-chip hybrid

23 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 23 Overall Plan View Junction cardsCooling bulkheadsPositioning bulkhead

24 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 24 Parameters Comparing channel count: 2a: channels 2b: channels Cable plant is slightly smaller than in Run2a

25 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 25 Performance Expected performance of new tracker compared with 2a tracker Z bbar WH l bbar Mistag rate 1-2% Single muons

26 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 26 Cost Total M&S Project cost of $8.1 M, without contingency Cost estimate carried out down to WBS level 5 Estimate has changed very little since first estimate »$6.8M ($10.0M) April 01 Cost drivers »Silicon sensors »Cables, analogue, digital and twisted pair in near equal amounts »Hybrids

27 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 27 Near Term Start Dates Complete resource loaded schedule being prepared Some near term start dates / milestones Submitted to ELMA Ready for submission

28 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 28 Fallback The design adequately addresses the physics goals of Run2b Emphasis on impact parameter measurement at small radii Minimum of four stereo measurements needed for efficient pattern recognition The design is a conservative, not overextended design As such, any descoping would adversely affect physics performance We believe we can build this device within the time frame proposed, given adequate support Considered what if scenarios Modularity »Inner and outer barrel, north and south tracker built as independent units Branch points »Assess viability of various design choices »Assess impact of delivery schedule for various components Branch points will have to be developed in the near future

29 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 29 Summary and Conclusions The design of the Run2b silicon detector is solid Adequately addresses the physics issues Design not overextended Schedule is aggressive, but achievable we believe We are in a position to start ordering prototypes for various elements Delay in procurement will result in linear delay of project The collaboration is committed to building the new detector; if the project is endorsed, we are looking for a similar commitment from the laboratory

30 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 30 Boundary Conditions: spatial Silicon tracker to be installed within existing fiber tracker, with inner radius of 180 mm Full tracking coverage Fiber tracker up to | | < 1.6 Silicon stand-alone up to | | < 2.0 Installation in collision hall p Tracker will be split at z=0 Two independent half-modules Reproducible mount at z=0 Alignment verified at SiDet Installation of beampipe after tracker installation There will be a 3mm gap from sensor to sensor at z=0

31 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 31 Luminous Region Addresses uncertainty on evolution of beam size over the course of a store Assumed beam crossing centered at z=0; no uncertainties folded in Coverage of inner layers of 100 cm results in loss of < ~2% of integrated luminosity Length of inner layer set at 96 cm From M. Church p Luminosity acceptance of detector in Run2b running conditions Longitudinal emittance 2, 3 eV-sec Stacking rate 40, 60 E10/hr Assumptions: * = 35 cm Trans..mm.mrad 0.5 crossing angle 136 rad

32 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 32 Boundary Condition: DAQ Retain readout system downstream of adapter card Cable plant allows for 912 low mass / high mass cables Central silicon: 720 H disks: 192 Total number of readout modules cannot exceed 912 3/6/8/9 Chip HDI Sensor 8 Low Mass Cable ~19-30 High Mass Cable (3M/80 conductor) HV / LV Adapter Card KSU Interface Board CLKs retain p Some changes to voltage distribution will have to be made

33 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 33 Irradiation Studies Irradiation studies carried out with ELMA sensors and CDF layer 00 sensors from Hamamatsu and Micron Measured I leak, V depl Measurements agree well with other measurements Calculate I leak, V depl and ENC for various Si temperatures to determine Si running temperature during operation Conclude that the design value for Silicon operating temperature at the inner layer should be T= -10 o C

34 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 34 Comparison 2a and 2b 2a: »Innermost radius 25.7 mm »Outermost radius 94.3 mm 2b: »Innermost radius 17.5 mm »Outermost radius mm End views drawn to scale

35 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 35 Design Choices Si temperature of inner layer should be kept at T=-10 o C Heat Load »~30 Watts ambient »~20 Watts at 15 fb -1 at innermost layer (T= -10 o C) »~0.5 Watts per readout chip Cooling will use 40%-60% water/ethylene-glycol mixture T clnt = -15 o C Option to go to T clnt = -20 o C with second chiller for inner layers Heat load too high to allow for readout chips to be mounted on silicon: analogue cables, off-board electronics for innermost layer Detector Hybrid Analogue cable Digital cable DØ L0 CDF layer 00 Analogue cables

36 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 36 Inner Layers Inner two layers have 12-fold crenellated geometry with carbon fiber lined, carbon foam support structure Layer 0 2-chip wide sensors, 25 m pitch, 50 m readout Analogue cables for readout Hybrids off-board R in = 17.8 mm Layer 1 3-chip wide sensors, 58 m pitch, axial readout Hybrids on-board 6-chip hybrid readout R in = 34.8 mm Cooling channel Silicon sensor Analogue cable stack

37 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 37 SVX4 Chip Nov 00 decision to employ common readout chip for CDF and DØ SVX4 in deep sub-micron, 0.25 m technology, intrinsically rad-hard »Brand new chip with own personality/features Commercial foundries used That CDF and DØ will use the exact same chip is now very likely Recently decided to use the same padring Test chip submitted to MOSIS 06/04/01 16 channels LBL design preamp + pipeline 48 channels FNAL design preamp + pipeline »Common bias preamp+pipeline as in SVX3 »12 different input transistor sizes used to optimize noise Results: »Some problems with the chip but they are all understood »ENC = 450e e/pF (optimum) »Pipeline works LBL Pre-amp FNAL Pre-amp Pipeline

38 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 38 SVX4 Chip Progress this week: Fermilab pre-amp will be implemented in final version of chip Fermilab has full responsibility for the entire FE Issues: There still remains some concern by LBL about the on-chip bypassing Work on the BE still remains A lot of integration work still remains Schedule has slipped by about 2 months since last year Schedule: Anticipated submission of the full chip by the end of October Should have full production chips by end of the year Recall, DØ uses the chip in SVX2 mode Uses single clock for FE and BE, incurs deadtime SVX2 signals single-ended Decided to drive the chip differential

39 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 39 Inner Layers: layer 0 Hybrids are off board 2-chip hybrids Staggered in z for 6 readouts per end per phi-sector Space is extremely tight ! Analogue cables Cooling lines Hybrids Digital cable stack

40 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 40 Schedule Complete resource loaded schedule being prepared

41 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 41 Why no 90-degree Stereo Issues: Due to multiplexing of signals more difficult pattern recognition; more fakes Large incident angles, large number of strips hit »Preferentially use thinner silicon to partially compensate Fraction of tracks that have a close neighbor is rather high »Need to resort to splitting shared clusters Requires double-metal layer; HPK no experience with dm layers on 6 wafers No definitive answer yet from Run2a data We have confidence that we can achieve our physics goals with the current design Of course, 3d-vertex gives additional information, but has to be compared to additional requirements Complicates design, more sensor types, more testing, probing, more manpower, … DØ made conscientious decision not to adopt 90-degree stereo readout given manpower and time constraints

42 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 42 Layer 0 p Hybrids are off board Analogue cables carry signals 2-chip hybrids Staggered in z for 6 readouts per end per phi-sector p Space is extremely tight ! Hybrid Digital cable Stiffening ribs p Six support rings Holds hybrids Provides heat flow path p Six stiffening ribs

43 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 43 Sensor lengths Inner layers: 79.4 mm, 6 sensors per half-module Outer layers: 100 mm, 5 or 6 sensors per half-module Longitudinal segmentation Indicating readout by length of readout segment: »L0, L1: each sensor readout »L2, L3: readout »L4, L5: readout Governed by: »Number of allowed readout cables »Occupancy, cluster sharing Hybrids are double-ended, i.e service out two readout segments, indicated by the length of the respective readout segments: 10-10, 10-20, Design Choices Z=0Z (mm)

44 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 44 Analogue Flex Cables Low mass, fine pitch cables to bring analogue signals outside of tracking volume Technically challenging »Feature size ~ 3-4 m »C ~ 0.4 pF/cm Dyconex (Switzerland) Delivered 2 pre-prototype cables »128 channels, trace width 6-7 m »13.7 mm of 50 m pitch traces »26.0 mm of 100 m pitch traces »fan-in and fan-out region ( mm) »total trace length including fan-in/out between 41.4 – 42.6 mm »2 rows of bond pads on each side »No gold plating yet Results so far are very encouraging »Only 3 opens, no shorts »Uniform characteristics across cable Detector Hybrid Analogue cable Digital cable DØ L0

45 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 45 Design Considerations Do not compromise on the performance of the Run2a silicon tracker Choose design adequate to achieve physics goals (no 90-degree stereo), but do not over-design Provide stand-alone tracking up to | | < 2.0 Modular design, minimize the number of different elements Use established technologies Divide tracker in two radial groups: Inner layers »Design to withstand integrated luminosity of 15 fb -1, with adequate margin »Provide path for possible replacement of only innermost or both inner layers Outer layers »Design to last a long time

46 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 46

47 Fermilab PAC Meeting, April 12-14, M. Demarteau Slide 47 Layer 0 Support Structure Analysis Measurements and Comparisons of elastic properties of prepreg. laminates Strength of a variety of lay-ups, compared to theoretical predictions FEA analysis on prototype L0 structure simple supports at z = 0 and z =630 mm Maximum sagitta = 4.63 m C-fiber properties from UW test data 2/2/02 Inner tube: 0/90/0 lay-up Outer castellation: 0/+20/-20/-20/+20/0 lay-up Good agreement between measurement and prediction


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