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Embedded Systems Group (http://www.cse.iitd.ac.in/esproject) Department of Computer Science & Engineering Indian Institute of Technology Delhi June 11,

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Presentation on theme: "Embedded Systems Group (http://www.cse.iitd.ac.in/esproject) Department of Computer Science & Engineering Indian Institute of Technology Delhi June 11,"— Presentation transcript:

1 Embedded Systems Group (http://www.cse.iitd.ac.in/esproject) Department of Computer Science & Engineering Indian Institute of Technology Delhi June 11, 2002 Ph.D. Research Plan Presentation Anup Gangwar

2 Slide 2 Research Plan Presentation, June 11, Presentation Outline Introduction and motivation Specialization opportunities in VLIW processors Methodology Validation framework (supporting tools required) Work plan Status of work References

3 Slide 3 Research Plan Presentation, June 11, Introduction Why customize architectures? General purpose computing domain Vs embedded Customization leads to cheaper design solutions Architectural choices for exploiting ILP Superscalar processors Try to extract ILP at run time, so, complex hardware Limited clock speeds and high power dissipation Not suited for embedded type of applications VLIW processors Compiler has lot of knowledge about hardware Compiler extracts ILP statically, so, simplified hardware Possible to attain higher clock speeds

4 Slide 4 Research Plan Presentation, June 11, Introduction - Problems with VLIW Processors Complex compiler required for extracting ILP Adequate hardware support needed for compiler controlled execution Code size expansion due to explicit NOPs if, The application does not contain enough parallelism The compiler is not able to extract parallelism from the application Need for good instruction encoding and NOP compression schemes

5 Slide 5 Research Plan Presentation, June 11, Presentation Outline Introduction and motivation Specialization opportunities in VLIW processors Methodology Validation framework (supporting tools required) Work plan Status of work References

6 Slide 6 Research Plan Presentation, June 11, Specialization Opportunities -> FUs

7 Slide 7 Research Plan Presentation, June 11, Specialization Opportunities -> FUs (contd...) Functional Unit Types MISO or Multiple Input Single Output MIMO or Multiple Input Multiple Output MIMO with LD/ST or MIMOs with memory interaction Rigid or flexible I/O timeshapes

8 Slide 8 Research Plan Presentation, June 11, Specialization Opportunities -> Reg. File Single register file organization doesnt scale well Area grows as N 3 Delay grows as N 3/2 Power grows as N 3 where N is the no. of Functional Units connected to the register file Clustered VLIW architectures are the solution Each FU can read from/write to only a subset of registers Data copying may increase execution latency Powerful application analysis required to overcome above mentioned problems

9 Slide 9 Research Plan Presentation, June 11, Specialization Opportunities -> Reg. File (contd...) A Clustered VLIW Architecture

10 Slide 10 Research Plan Presentation, June 11, Specialization Opportunities -> Interconnect Clustering FUs together requires deciding ICN between different clusters between clusters and memory Analysis of data access patterns required for evaluating cost-performance tradeoffs Current ASIP vendors do not offer customizable interconnects

11 Slide 11 Research Plan Presentation, June 11, Specialization Opportunities -> Encoding Instruction encoding/decoding scheme affects Code size Object code compatibility Branch miss prediction penalty Hardware cost Address specification in code size Each UniOp is equivalent to a RISC/CISC instruction UniOp MultiOp

12 Slide 12 Research Plan Presentation, June 11, Specialization Opportunities -> Encoding (contd...) ADDNOPFMULNOP IALU.0IALU.1FALU.0BU.0 NOPs in a MultiOp VLIW Processor Pipeline with Instruction Decompressor

13 Slide 13 Research Plan Presentation, June 11, Specialization Opportunities -> Summary

14 Slide 14 Research Plan Presentation, June 11, Presentation Outline Introduction and motivation Specialization opportunities in VLIW processors Methodology Validation framework (supporting tools required) Work plan Status of work References

15 Slide 15 Research Plan Presentation, June 11, Existing Methodologies -> Simulation Driven

16 Slide 16 Research Plan Presentation, June 11, VLIW ASIP Synthesis Methodology Task Set and Constraints Architecture Description Architecture Design Space Exploration Application Parameter Extraction Retargetable Compiler Instruction Encoding Specialization Validation (Simulation with encoded instructions) Architecture Description (Output to synthesizer)

17 Slide 17 Research Plan Presentation, June 11, Presentation Outline Introduction and motivation Specialization opportunities in VLIW processors Methodology Validation framework (supporting tools required) Work plan Status of work References

18 Slide 18 Research Plan Presentation, June 11, Validation Framework -> Trimaran C Program IMPACT SIMULATOR Generator ELCOR Bridge Code ELCOR IR HMDES Machine Description Generated Simulator (Statistics) ANSI C Parsing Code profiling Classical machine independent optimizations Block formation Machine dependent code optimizations Code scheduling Register allocation ELCOR IR to low level C files HPL-PD virtual machine Cache simulation Performance statistics Compute and stall cycles Cache stats Spill code info

19 Slide 19 Research Plan Presentation, June 11, Validation Framework -> Trimaran (contd...) Code Processor Native Compiler REBEL HMDES Low level C filesC librariesEmulation Library Executable for the host platform

20 Slide 20 Research Plan Presentation, June 11, Validation Framework -> Retargetable Assembler Instruction Encoding Description Toolkit Generator Generated Assembler Assembly Instructions Object Code To Simulator (for simulation with encoded instructions)

21 Slide 21 Research Plan Presentation, June 11, Presentation Outline Introduction and motivation Specialization opportunities in VLIW processors Methodology Validation framework (supporting tools required) Work plan Status of work References

22 Slide 22 Research Plan Presentation, June 11, Work Plan -> Interconnect/RF/FU Specialization Initially model the interconnect problem as ILP and later on move to other solutions Code selection problem in compilers is similar to identifying compute intensive parts for AFUs No. and type of FUs has not been properly explored RF clustering problem has not been dealt with elsewhere Jacome et. al. Deal with Interconnect/RF/FU specialization simultaneously Operation chaining is not considered

23 Slide 23 Research Plan Presentation, June 11, Work Plan -> Encoding/Decoding Specialization Goal is to be able to generate encoding schemes automatically Work of Shail Aditya et. al. Basically a parameterized encoding scheme Techniques especially for HPL-PD architecture Do not talk of dynamic code size minimization Encoding template is fixed exploration limited only to within the template design space Various encoding templates need to be explored, also the template itself may be derived from application Dynamic code size minimization needs to be considered

24 Slide 24 Research Plan Presentation, June 11, Presentation Outline Introduction and motivation Specialization opportunities in VLIW processors Methodology Validation framework (supporting tools required) Work plan Status of work References

25 Slide 25 Research Plan Presentation, June 11, Work Status -> Specialized FUs in Trimaran Modeling MISOs Model as external function calls Replace in Trimaran bridge code and replace with AFU op Model new AFU in MDES with the required ops Introduce the semantics in simulator op definitions file Modeling MIMOs Model as external function calls returning voids Replace in Trimaran bridge code and replace with AFU op Explicitly reserve registers in C-code for returning values Introduce operation semantics in simulator op definition file

26 Slide 26 Research Plan Presentation, June 11, Work Status -> Specialized FUs in Trimaran (contd...) Modeling MIMOs with LD/ST Model as regular MIMOs Memory interaction with block LD/ST at beginning and end of execute cycles Additionally Possible to impose register file constraints Various I/O timeshapes, rigid or flexible Possible to introduce pipelined functional units

27 Slide 27 Research Plan Presentation, June 11, Work Status -> Instruction Enc. in Trimaran

28 Slide 28 Research Plan Presentation, June 11, Work Status -> Instruction Enc. in Trimaran (contd...) New Jersey Machine Code Toolkit (NJMC) Deals with bits at symbolic level Can be used to write assemblers/disassemblers Specification in SLED (Specification Language for Encoding/Decoding) Model instruction decompressor in HMDES Instrument ELCOR to generate assembly code Encoding is done using procedures generated by NJMC Problems with NJMC VLIW instruction need to be broken up into 32 bit tokens Encoded instructions must end on 8 bit boundary

29 Slide 29 Research Plan Presentation, June 11, Work Status -> Code Gen. for Clustered ASIPs ELCOR Disadvantages ELCOR is heavily oriented towards HPL-PD architecture Does not support clustered VLIW architecture Advantages Strong optimizing compiler Rich library to deal with the IR IMPACT compiler system offers another choice for building a backend Feasibility study being carried out to fix a particular direction of work

30 Slide 30 Research Plan Presentation, June 11, Presentation Outline Introduction and motivation Specialization opportunities in VLIW processors Methodology Validation framework (supporting tools required) Work plan Status of work References

31 Slide 31 Research Plan Presentation, June 11, References Bhuvan Middha, Varun Raj, Anup Gangwar, M. Balakrishnan, Anshul Kumar and Paolo Ienne, A Trimaran based framework for exploring design space of VLIW ASIPs with coarse grain FUs, ISSS Anup Gangwar, M. Balakrishnan and Anshul Kumar, A framework for studying the effect of VLIW processor instruction encoding and decoding schemes, Mini Project, Dept. of CSE. M. Jacome and G. de. Veciana, Design challenges for new application specific processors, IEEE Design and Test of Computers B. Ramakrishna Rau and Michael S. Schlansker, Embedded computer architecture and automation, IEEE Computer-2001 Michael S. Schlansker and B. Ramakrishna Rau, EPIC: An architecture for instruction-level parallel processors, HPCA N. G. Busa, A. van der Werf and M. Bekooij, Scheduling coarse grain operations for VLIW processors, ASPDAC Shail Aditya, Scott A. Mahlke and B. Ramakrishna Rau, Code size minimization and retargetable assembly for custom EPIC and VLIW processors, ISSS-1999.


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