B1011 Machine Code ENGR xD52 Eric VanWyk Fall 2012.

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b1011 Machine Code ENGR xD52 Eric VanWyk Fall 2012

Today Review Homework Translating Assembly to Machine Code Executing Machine Code Biggest Endian is Best Endian

Estimation Answers ranged from 3 seconds to many trillions of years, less than a cent to more than the cumulative global GDP for our lifetimes Lets use dimensional analysis to pull the range in a little bit…

Dimensional Analysis Target a specific unit with a series of translating scaling factors Make sure units cancel Super easy if everything is to the 1 st power

Fast Approximations Translate scaling factors to powers of 10 Add to multiply, subtract to divide Memorize your Log Tables log(8) =0.903log(5) =0.698 log(3) = 0.477log(2) = 0.301

Fast Approximations Translate scaling factors to powers of 10 Add to multiply, subtract to divide Memorize your Log Tables 8->E0.95 ->E0.7 3 -> E0.52 -> E0.3

Assumptions Made 1 billion tests per second – 10k to 10B is ok 20 Watts – 5 to 100 Watts is ok 10 cents per kWhr – Or whatever

Duration Number of Computations Computations / second Seconds / year Result in years (2^64): 64*.3 : 10^19.2 10^9 3*10^7 = 10^7.5 19.2-9-7.5 = 2.7

Cost Number of Seconds Seconds / hour Kilowatts (0.020) Dollars per kWhr Dollars 10^10.2 10^3.6? 10^(1.3-3=-1.7) 10^-1 10.2-3.6+(-1.7)+(-1) = 3.9

Results Time: Math = 584.5 years Estimate = 500 Error = -15% Ratio = 0.85 Log Error =.06ish Cost: Math = 10,248 dollars Estimate = 8,000 dollars Error = -22% Ratio = 0.78 Log Error =.1ish

Machine Code The actual bits sent to the processor

Encoding Limitations Designing an Encoding Scheme is a Game – Best use of limited space? – Favor some options over others Take Available Space and divide into Fields – Encoding within an Encoding (MOAR BOXES) – Fixed width per field – How many fields does IEEE-754 use?

Types of Fields Enumerations – No mathematical meaning, just enumerate options Signed / Unsigned – We know these well Biased – Mathematically offset by a constant

MIPS Code Encoding Formats All instructions encoded in 32 bits Register (R-type) instructions Immediate (I-type) instructions Jump (J-type) instructions 3130292827262524232221201918171615141312111009080706050403020100 OPRSRTRDSHAMTFUNCT 3130292827262524232221201918171615141312111009080706050403020100 OPRSRT16 bit Address/Immediate 3130292827262524232221201918171615141312111009080706050403020100 OP26 bit Address (OP = 0,16-20) (OP = any but 0,2,3,16-20) (OP = 2,3)

Multiple Encoding Formats? Make the most of our limited resources How do we know which format? Why bother re-using encodings at all?

J-Type Used for Unconditional Jumps Simplest MIPS encoding How do we encode j 100? 2: j (jump) 3: jal (jump and link) 3130292827262524232221201918171615141312111009080706050403020100 OP26 bit Address

J-Type Weirdness in the Address Field Bottom 2 bits are always 00, so dropem – Shift everything over by 2 Thats only 28 effective bits… – Where are the other 4? – How does this limit us? – How do we compensate?

I-Type Used for operations with immediate (constant) operand 3130292827262524232221201918171615141312111009080706050403020100 OPRSRT16 bit Address/Immediate 04:beq 05:bne 06:blez 07:bgtz 08:addi 09:addiu 10:slti 11:sltiu 12:andi 13:ori 14:xori 32:lb 35:lw 40:sb 43:sw Op1, L/S addr Op2, Dest, L/S targ

I-Type Used for ops with an immediate operand One Op Field (Enumeration) Two register address fields One Signed/Unsigned field 3130292827262524232221201918171615141312111009080706050403020100 OPRSRT16 bit Address/Immediate

I-Type Examples 04:beq 05:bne 06:blez 07:bgtz 08:addi 09:addiu 10:slti 11:sltiu 12:andi 13:ori 14:xori 32:lb 35:lw 40:sb 43:sw addi\$t0, \$t1, 100# \$t0 = \$t1+100 3130292827262524232221201918171615141312111009080706050403020100 beq\$a0, \$a1, -44# if \$a0 == \$a1 GOTO (PC+4+FOO*4) 3130292827262524232221201918171615141312111009080706050403020100 lw\$t3, 12(\$t0)# \$t3 = Memory[\$t0+12] 3130292827262524232221201918171615141312111009080706050403020100

I-Type Examples 04:beq 05:bne 06:blez 07:bgtz 08:addi 09:addiu 10:slti 11:sltiu 12:andi 13:ori 14:xori 32:lb 35:lw 40:sb 43:sw addi\$t0, \$t1, 100# \$t0 = \$t1+100 3130292827262524232221201918171615141312111009080706050403020100 addi\$t1\$t0100 beq\$a0, \$a1, -44# if \$a0 == \$a1 GOTO (PC+4+FOO*4) 3130292827262524232221201918171615141312111009080706050403020100 beq\$a1\$a0-11 lw\$t3, 12(\$t0)# \$t3 = Memory[\$t0+12] 3130292827262524232221201918171615141312111009080706050403020100 lw\$t0\$t312

I-Type Examples 04:beq 05:bne 06:blez 07:bgtz 08:addi 09:addiu 10:slti 11:sltiu 12:andi 13:ori 14:xori 32:lb 35:lw 40:sb 43:sw addi\$t0, \$t1, 100# \$t0 = \$t1+100 3130292827262524232221201918171615141312111009080706050403020100 898100 beq\$a0, \$a1, -44# if \$a0 == \$a1 GOTO (PC+4+FOO*4) 3130292827262524232221201918171615141312111009080706050403020100 454-11 lw\$t3, 12(\$t0)# \$t3 = Memory[\$t0+12] 3130292827262524232221201918171615141312111009080706050403020100 0x2381112

R-Type Used for 3 register ALU operations 3130292827262524232221201918171615141312111009080706050403020100 OPRSRTRDSHAMTFUNCT 00:sll 02:srl 03:sra 04:sllv 06:srlv 07:srav 08:jr 24:mult 26:div 32:add 33:addu 34:sub 35:subu 36:and 37:or 38:xor 39:nor 42:slt 00 (10-13 for FP) Shift amount (0 for non-shift) add\$8, \$9, \$10# \$8 = \$9+\$10 sll\$8, \$9, 6# \$8 = \$9<<6 sllv\$8, \$9, \$10# \$8 = \$9<<\$10 Op2Op1 Dest 3130292827262524232221201918171615141312111009080706050403020100 9108032 3130292827262524232221201918171615141312111009080706050403020100 X986 3130292827262524232221201918171615141312111009080706050403020100 1098004

Decoding The Instruction Decode Unit translates the encoded Machine Code into control signals Lets (begin to) figure out the Decode Unit by creating (part of) its truth tables To finish, wed apply Boolean Law and push the design all the way through to gates

26 Our Single Cycle CPU SignExtnd WrEn Addr Din Dout Data Memory Instruction Fetch Unit Rs Rt RsRtRdImm16 imm16 Instructions[31:0] [25:21][20:16][15:11] [15:0] Branch Jump ALUSrc RegDst RdRt ALUcntrl Aw Aa Ab Da Dw Db Register WrEn File RegWr MemWr MemToReg Zero

Design Your Own Encodings Memorizing MIPS encodings is super fun, but lets make up our own instead! Use the single cycle cpu as a starting point – Modify as necessary to suit your goals Come up with an interesting tweak to the design and see it all the way through

Design Your Own Encodings Ideas: – What can you fit into a 16 bit Machine Code? – Can you add support for ARM-like shifting? – What about variable length encodings? Tools / Tweaks: – How many Registers do you support? – Are some ops redundant? – Nothing is sacred today

Design Your Own Deliverables 2 sentences on your idea Description of supported operations Description of encoding styles White Board Schematic of modified CPU Assemble, Encode, Decode a small example program to highlight your idea

31 Our Single Cycle CPU SignExtnd WrEn Addr Din Dout Data Memory Instruction Fetch Unit Rs Rt RsRtRdImm16 imm16 Instructions[31:0] [25:21][20:16][15:11] [15:0] Branch Jump ALUSrc RegDst RdRt ALUcntrl Aw Aa Ab Da Dw Db Register WrEn File RegWr MemWr MemToReg Zero