Presentation on theme: "CS1104 – Computer Organization Aaron Tan Tuck Choy School of Computing National University."— Presentation transcript:
CS1104 – Computer Organization Aaron Tan Tuck Choy School of Computing National University of Singapore
CS Lecture 14: Introduction to Algorithmic State Machines (ASM) 2 Large Digital Systems Top-Down Approach Controller and Data Processor Flowcharts ASM Charts Components of ASM Charts ASM Charts: An Example Register Operations Timing in ASM Charts
CS Lecture 14: Introduction to Algorithmic State Machines (ASM) 3 ASM Charts => Digital System ASM Charts => Digital System ASM Charts => Controller ASM Charts => Controller ASM Charts => Architecture/Data Processor ASM Charts => Architecture/Data Processor Implementing the Controller With JK Flip-flops Decoder + D flip-flops One Flip-flop per State Multiplexers PLA/ROM
CS Large Digital Systems4 In both combinational and sequential circuit design: small circuits via gate-level design (truth tables, K maps, etc) large circuits via block-level design (MSI components, etc.) However, larger digital systems need more abstract and systematic design techniques. One such systematic design method has the following characteristics: top-down approach separation of controller from controlled hardware develop an overall architecture (at block levels) before proceeding into the details of hardware.
CS Top-Down Approach5 Top-down approach is immensely important for large complex system (whether hardware, software, or manual systems). Emphasis on macroscopic view, starting from original problem and gradually refine it towards solution. Steps for a top-down design procedure: Specify the problem clearly (at global/top level without unnecessary details). Break the problem into smaller sub-problems. Repeat the process until subproblems are small enough to be solved directly (implementable).
CS Top-Down Approach6 Corresponds to goal-directed approach. State goal, then find sub-goals to solve main goal. Repeat until sub-goals are directly solvable. Pass CS1103 Do TutorialsPass TestsPass Exam Ask questionsPracticeReviseSleep well
CS Controller & Data Processor7 Digital systems are typically processors of information. They store data through flip-flops, registers and memory, and process them using combinational circuits like adders, multipliers, etc. These processing may pass through complicated sequences.
CS Controller & Data Processor8 A digital system consists of two components A control algorithm (controller) and An architecture (data processor) Control unit (Controller) Data Processor (Architecture) Commands Input data External command Status condition Output data
CS Controller & Data Processor9 Separation of the controller operations from the data processing operations Control operations give commands that direct the data processing operations to accomplish the desired tasks. Data processing operations manupulates the data according to requirements. A mechanical analogy: Automobile. Car (data processor): transports people from one location to another. Driver (controller): gives instructions to car to achieve objective.
CS Flowcharts10 Flowcharts Flowcharts: a tool for precise description of algorithms/procedures. Specify tasks to perform and their sequencing. Main symbols: Operation box: contains tasks/operations to perform. Decision box: alternative actions based on decisions to be taken. Arrows: indicate appropriate sequencing.
CS Flowcharts11 Flowcharts An operation box is rectangular in shape, and is used to specify one or more subtasks to be performed. It has at most one entry point and one exit point. Sub-task or operation to perform
CS Flowcharts12 Flowcharts A decision box is diamond-shaped. It has one entry point and multiple (but mutually exclusive) exit points. choice option Aoption Boption C
CS Flowcharts13 Flowcharts Sequential flow: simplest type of sequencing; tasks are done in sequential order. An example: Eating a 3-course Western meal. Drink soup Main course Eat dessert Boxes are connected by lines with arrows. Lines without arrows are sometimes used. In the absence of arrows, the default flow direction is top-to-bottom and left-to-right.
CS Flowcharts14 Flowcharts Iteration: some tasks/operations may be repeatedly/iteratively done. This is achieved through the loop-back in the flowchart. Decision box is used to determine when to terminate the loop.
CS Flowcharts15 Flowcharts An example: Eating a Western meal in oriental style. Drink soup Main course Eat dessert enough? yes no
CS Flowcharts16 Flowcharts Flowcharts can be used to implement complex decisions. get BF to buy nice colour & style? yes no reject test out affordable? made in Europe? yes no fitting? BFs opinion? accep- table poor encouraging insulting no
CS ASM Charts17 ASM Charts Algorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware algorithms in digital systems. Major differences from flowcharts are: uses 3 types of boxes: state box (similar to operation box), decision box and conditional box contains exact (or precise) timing information; flowcharts impose a relative timing order for the operations. From the ASM chart it is possible to obtain the control the architecture (data processor)
CS Components of ASM Charts18 Components of ASM Charts The state box is rectangular in shape. It has at most one entry point and one exit point and is used to specify one or more operations which could be simultaneously completed in one clock cycle. one or more operations state binary code
CS Components of ASM Charts19 Components of ASM Charts The decision box is diamond in shape. It has one entry point but multiple exit points and is used to specify a number of alternative paths that can be followed. deciding factors
CS Components of ASM Charts20 Components of ASM Charts The conditional box is represented by a rectangle with rounded corners. It always follows a decision box and contains one or more conditional operations that are only invoked when the path containing the conditional box is selected by the decision box. conditional operations
CS ASM Charts: An Example21 ASM Charts: An Example An example: Initial state S A 0 F 0 A A + 1 A2A2 E 0E 1 A3A3 F T2T2 T1T1 T0T0 A is a register; A i stands for i th bit of the A register. A = A 4 A 3 A 2 A 1 E and F are single- bit flip-flops.
CS Register Operations22 Register Operations Registers are present in the data processor for storing and processing data. Flip-flops (1-bit registers) and memories (set of registers) are also considered as registers. The register operations are specified in either the state and/or conditional boxes, and are written in the form: destination register function(other registers) where the LHS contains a destination register (or part of one) and the RHS is some function over one or more of the available registers.
CS Register Operations23 Register Operations Examples of register operations: A BTransfer contents of register B into register A. A 0Clear register A. A A 1Decrement register A by 1.
CS Timing in ASM Charts24 Timing in ASM Charts Precise timing is implicitly present in ASM charts. Each state box, together with its immediately following decision and conditional boxes, occurs within one clock cycle. A group of boxes which occur within a single clock cycle is called an ASM block.
CS Timing in ASM Charts25 Timing in ASM Charts 3 ASM blocks Initial state S A 0 F 0 A A + 1 A2A2 E 0E 1 A3A3 F T2T2 T1T1 T0T0
CS Timing in ASM Charts26 Timing in ASM Charts Operations of ASM can be illustrated through a timing diagram. Two factors which must be considered are operations in an ASM block occur at the same time in one clock cycle decision boxes are dependent on the status of the previous clock cycle (that is, they do not depend on operations of current block)
CS Timing in ASM Charts27 Timing in ASM Charts Operations A 0 F 0 A A+1 E 0 A A+1 E 0 A A+1 E 1 A A+1 E 1 A A+1 E 0 A A+1 E 0 A A+1 E 1 F 1 A = A 4 A 3 A 2 A 1
CS Timing in ASM Charts28 Timing in ASM Charts A = A 4 A 3 A 2 A 1 Initial state S A 0 F 0 A A + 1 A2A2 E 0E 1 A3A3 F T2T2 T1T1 T0T0 Operations A 0 F 0 A A+1 E 0 A A+1 E 0 A A+1 E 1 A A+1 E 1 A A+1 E 0 A A+1 E 0 A A+1 E 1 F 1 Operations
CS ASM Chart => Digital System29 ASM Chart => Digital System ASM chart describes a digital system. From ASM chart, we may obtain: Controller logic (via State Table/Diagram) Architecture/Data Processor Design of controller is determined from the decision boxes and the required state transitions. Design requirements of data processor can be obtained from the operations specified with the state and conditional boxes.
CS ASM Chart => Controller30 ASM Chart => Controller Procedure: Step 1: Identify all states and assign suitable codes. Step 2: Draw state diagram. Step 3: Formulate state table using State from state boxes Inputs from decision boxes Outputs from operations of state/conditional boxes. Step 4: Obtain state/output equations and draw circuit.
CS ASM Chart => Controller31 ASM Chart => Controller Initial state S A 0 F 0 A A + 1 A2A2 E 0E 1 A3A3 F T2T2 T1T1 T0T0 T0T0 T1T1 T2T2 Assign codes to states: T 0 = 00 T 1 = 01 T 2 = 11 Inputs from conditions in decision boxes. Outputs = present state of controller.
CS ASM Chart => Architecture/Data Processor 32 ASM Chart => Architecture/Data Processor Architecture is more difficult to design than controller. Nevertheless, it can be deduced from the ASM chart. In particular, the operations from the ASM chart determine: What registers to use How they can be connected What operations to support How these operations are activated. Guidelines: always use high-level units simplest architecture possible.
CS ASM Chart => Architecture/Data Processor 33 ASM Chart => Architecture/Data Processor Various operations are: Counter incremented (A A + 1) when state = T 1. Counter cleared (A 0) when state = T 0 and S = 1. E is set (E 1) when state = T 1 and A 2 = 1. E is cleared (E 0) when state = T 1 and A 2 = 0. F is set (F 1) when state = T 2. Deduce: One 4-bit register A (e.g.: 4-bit synchronous counter with clear/increment). Two flip-flops needed for E and F (e.g.: JK flip-flops).
CS ASM Chart => Architecture/Data Processor 34 ASM Chart => Architecture/Data Processor Controller K J Q K J Q Clk 4-bit syn. counter A A2A2 A1A1 A2A2 A3A3 A3A3 A4A4 start S E F clock CP count clear T2T2 T1T1 T0T0 (A A + 1) when state = T 1. (A 0) when state = T 0 and S = 1. (E 1) when state = T 1 and A 2 = 1.
CS Implementing the Controller35 Implementing the Controller Once the state table is obtained, the controller can be implemented using one of these techniques. 1. Traditional method: With JK flip-flops. design done at gate level. suitable for small controllers. procedure: prepare state table, use K-maps to obtain next- state/output functions. 2. Decoder + D flip-flops suitable for moderately large controllers. procedure: use decoder to obtain individual states; from the state table, obtain the next-state functions by inspection.
CS Implementing the Controller36 Implementing the Controller 3. Multiplexers a more structured approach to implement controller. suitable for moderately large controllers. three level structure: vfirst level consists of multiplexers that determine the next state of the register; vsecond level is a register that holds the present state; vthird level has a decoder to provide separate output for each controller state.
CS Implementing the Controller37 Implementing the Controller 4. One flip-flop per state also known as One-Hot Spot Method of ASM synthesis. procedure: allocate one flip-flop per state; from state table, determine the formulae to set each flip-flop; must ensure that controller is properly initialised. 5. PLA/ROM highly regular approach. ROM approach uses a very simple table lookup technique but suffers from large number of dont care states. PLA can handle dont care states well but design method is still at gate-level.
CS Implementing Controller: With JK Flip-flops 38 Implementing Controller: With JK Flip-flops State table obtained from ASM chart: Corresponding state table using JK flip-flops:
CS Implementing Controller: Decoder + D Flip-flops 39 Implementing Controller: Decoder + D Flip-flops The flip-flop input functions can be obtained directly from the state table by inspection. This is because for the D flip-flops, the next state = flip-flop D input. Decoder is then used to provide signals to represent different states. D Q D Q 2x4 decoder T0T0 T1T1 T2T2 unused G1G1 G0G0 ? ? clock
CS Implementing Controller: Decoder + D Flip-flops 40 Implementing Controller: Decoder + D Flip-flops Given the state table: We can directly determine the inputs of the D flip- flops for G 1 and G 0. DG 1 = T 1.A 2.A 3 DG 0 = T 0.S + T 1
CS Implementing Controller: Decoder + D Flip-flops 41 Implementing Controller: Decoder + D Flip-flops Flip-flop input functions: DG 1 = T 1.A 2.A 3 DG 0 = T 0.S + T 1 Circuit: D Q D Q 2x4 decoder T0T0 T1T1 T2T2 unused G1G1 G0G0 clock A2A2 A3A3 S
CS Implementing Controller: One Flip- flop per State 42 Implementing Controller: One Flip-flop per State Require n flip-flops for n states; each flip-flop represents one state. (Other methods: n flip-flops for up to 2 n states.) D Q D Q T1T1 T0T0 ? ? clock ::::
CS Implementing Controller: One Flip- flop per State 43 Implementing Controller: One Flip-flop per State Formulae for next state can be obtained directly from state table: 1.If there is only one line going into the state, then formula = input condition ANDed with the previous state. 2.If there are more than one line, then formula = Ored of all the conditions found in (1).
CS Implementing Controller: One Flip- flop per State 44 Implementing Controller: One Flip-flop per State State table: State diagram: T0T0 S=0A 2 =0 T1T1 S=1 A 2 =1, A 3 =0 T2T2 A 2 =1, A 3 =1 Flip-flop input functions: DT 0 = T 2 + S'.T 0 DT 1 = S.T 0 + A 2 '.T 1 + A 2.A 3 '.T 1 = S.T 0 + (A 2.A 3 )'.T 1 DT 2 = A 2.A 3.T 1
CS Implementing Controller: One Flip- flop per State 45 Implementing Controller: One Flip-flop per State Circuit diagram below. To initialise to state T 0, set flip-flop of T 0 to 1 and clear the rest to zero. DT 0 = T 2 + S'.T 0 DT 1 = S.T 0 + (A 2.A 3 )'.T 1 DT 2 = A 2.A 3.T 1 D Q T1T1 T0T0 S clock D Q D Q T2T2 A2A3A2A3 clear preset
CS Implementing Controller: One Flip- flop per State 46 Implementing Controller: One Flip-flop per State Alternative: Use Q' output for T 0, and input function for T 0 is complemented. To initialise, clear all flip- flops to zero. DT 0 = (T 2 + S'.T 0 )' DT 1 = S.T 0 + (A 2.A 3 )'.T 1 DT 2 = A 2.A 3.T 1 D Q T1T1 T0T0 S clock D Q D Q T2T2 A2A3A2A3 clear Q'
CS Implementing Controller: Multiplexers 47 Implementing Controller:Multiplexers Purpose of multiplexer is to produce an input to its corresponding flip-flop equals to the value of the next state. The inputs of multiplexers are determined from the decision boxes and state transitions in the ASM chart.
CS Implementing Controller: Multiplexers 48 Implementing Controller:Multiplexers Example 1: Given the state table. Reformat the state table.
CS Implementing Controller: Multiplexers 50 Implementing Controller:Multiplexers Draw circuit: T1T1 T0T0 S clock D Q D Q T2T2 A2A3A2A3 2x4 decoder G1G1 G0G0 MUX S 1 S 0 MUX S 1 S Determine next state of register Hold present state
CS Implementing Controller: Multiplexers 51 Implementing Controller:Multiplexers Example 2: w 0 1 T0T0 00 T1T1 01 x 10 T3T3 11T2T2 10 y 10 y 01 z 10 z 01
CS Implementing Controller: Multiplexers 52 Implementing Controller:Multiplexers T1T1 T0T0 w clock D Q D Q T3T3 yzyz 2x4 decoder G1G1 G0G0 MUX S 1 S 0 MUX S 1 S 0 y' y 0 x' 1 y z' T2T2
CS Implementing Controller: PLA/ROM 53 Implementing Controller: PLA/ROM Similar to the design using D flip-flops and a decoder. The only difference is PLA essentially replaces the decoder and all the gates in the inputs of the flip- flops. PLA/ROM External command Commands to architecture Present state Next state Register to represent states