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TOPIC : Partition Technique UNIT 3 : VLSI Testing Module 3.4: Functional Testing

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Partition Technique The previous technique is not applicable to total- dependence circuits in which at least one PO depends on all PIs. In case of total-dependence circuits, we can use partitioning technique. The principle is to partition the circuit into segments. The inputs of the segment may not be PIs and the outputs may not be POs. To control the segment inputs from PIs and to observe its outputs, we use path sensitization.

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Contd … The steps involved in partitioning technique are: Segmentation – partitioning the circuit Representing each segment by its functional model Combining the vectors in each of these functional models into compact truth table. This process can be easily explained by an example.

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Example Apply the mentioned steps to this example. No. of inputs=6, so 2 6 =64 vectors are needed to test this circuit exhaustively. The test size can be reduced by using partitioning technique.

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Contd … Partition the given circuit into four segments as shown. To test segment2 exhaustively, we need 8 vectors and for the output h to propagate to PO y, we need f to be 1. So the table starts with these values No.abcdefghxy 1000111 2001111 3010111 4011100 5100111 6101111 7110111 8111111

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Contd … Now, to test segment1 we need 4 vectors and for its output g to propagate to PO x, we need h=1. If we observe in the table h=1 from 5 th to 8th vector, so we can use those rows to test segment1. No.abcdefghxy 1000111 2001111 3010111 4011100 50010010101 60110111111 71011011111 81111111111

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Contd … To test segment4: 2 out of 4 vectors are already covered in the table, so add the other two vectors (f,h)={00,01} to the table. Sensitize primary inputs for h=0 and h=1. No.abcdefghxy 1000111 2001111 3010111 4011100 50010010101 60110111111 71011011111 81111111111 9011000 10011010

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Contd … To test segment3: if we observe the table (g,h)={00,10} are missing. Its output is PO, so no need to take care of propagation to PO. Sensitize the primary inputs for g=0 and g=1. No.abcdefghxy 1000111 2001111 3010111 40001110000 50010010101 60110111111 71011011111 81111111111 90101101000 10011010

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Contd … The unfilled blocks can be any value. They are dont cares. In the table one can see that all the test cases for each gate have been covered. Partitioning technique has reduced the test size of the given circuit from 64 to 10 to test the circuit exhaustively.

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Figure 5–5 Exclusive-OR logic diagram and symbols. Open file F05-05 to verify the operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by.

Figure 5–5 Exclusive-OR logic diagram and symbols. Open file F05-05 to verify the operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by.

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