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II Extreme Models Study the two extremes of parallel computation models: Abstract SM (PRAM); ignores implementation issues Concrete circuit model; incorporates hardware details Everything else falls between these two extremes Topics in This Part Chapter 5 PRAM and Basic Algorithms Chapter 6 More Shared-Memory Algorithms Chapter 7 Sorting and Selection Networks Chapter 8 Other Circuit-Level Examples

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7 Sorting and Selection Networks Become familiar with the circuit model of parallel processing: Go from algorithm to architecture, not vice versa Use a familiar problem to study various trade-offs Topics in This Chapter 7.1 What is a Sorting Network? 7.2 Figures of Merit for Sorting Networks 7.3 Design of Sorting Networks 7.4 Batcher Sorting Networks 7.5 Other Classes of Sorting Networks 7.6 Selection Networks

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7.1 What is a Sorting Network? Fig. 7.1 An n-input sorting network or an n-sorter. Fig. 7.2 Block diagram and four different schematic representations for a 2-sorter.

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2-sorter Building Blocks for Sorting Networks Fig. 7.3 Parallel and bit-serial hardware realizations of a 2-sorter. Implementation with bit-parallel inputs Implementation with bit-serial inputs

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Proving a Sorting Network Correct Fig. 7.4 Block diagram and schematic representation of a 4-sorter. Method 1: Exhaustive test – Try all n! possible input orders Method 2: Ad hoc proof – for the example above, note that y 0 is smallest, y 3 is largest, and the last comparator sorts the other two outputs Method 3: Use the zero-one principle – A comparison-based sorting algorithm is correct iff it correctly sorts all 0-1 sequences (2 n tests)

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Validating a Sorting Network Stick diagram schematic b a d c Track 1 Track 2 Track 3 Track 4 min(a, b) max(a, b) min(c, d) max(c, d) min(a, b, c, d) max(a, b, c, d) ???? In the example above, it was fairly easy to show the validity of the sorting network. Generally, it is much more difficult How would one establish the validity of this 16-input sorting network? More importantly, how does one come up with this design in the first place?

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The Zero-One Principle 00000000 00000000 00010001 00010001 00100010 00010001 00110011 00110011 01000100 00010001 01010101 00110011 01100110 00110011 01110111 01110111 10001000 00010001 10011001 00110011 10101010 00110011 10111011 01110111 11001100 00110011 11011101 01110111 11101110 01110111 11111111 11111111 A sorting net built of comparators is valid if it correctly sorts all 0-1 sequences So, we can validate a sorting network using 2 n rather than n! input patterns n = 12: 2 n = 4096, n! = 479,001,600 (thousands vs. half a billion)

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Elaboration on the Zero-One Principle Deriving a 0-1 sequence that is not correctly sorted, given an arbitrary sequence that is not correctly sorted. Let outputs y i and y i+1 be out of order, that is y i > y i+1 Replace inputs that are strictly less than y i with 0s and all others with 1s The resulting 0-1 sequence will not be correctly sorted either

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7.2 Figures of Merit for Sorting Networks Delay: Number of levels Cost: Number of comparators Cost Delay In the following example, we have 5 comparators The following 4-sorter has 3 comparator levels on its critical path The cost-delay product for this example is 15 Fig. 7.4 Block diagram and schematic representation of a 4-sorter.

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Cost as a Figure of Merit Fig. 7.5 Some low-cost sorting networks.

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Delay as a Figure of Merit Fig. 7.6 Some fast sorting networks. These 3 comparators constitute one level

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Cost-Delay Product as a Figure of Merit Fast 10-sorter from Fig. 7.6 Low-cost 10-sorter from Fig. 7.5 Cost Delay = 29 9 = 261Cost Delay = 31 7 = 217 The most cost-effective n-sorter may be neither the fastest design, nor the lowest-cost design Applications of sorting networks: Directing information packets to their destinations in a network router Connecting n processors to n memory modules in a parallel computer

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7.3 Design of Sorting Networks Fig. 7.7 Brick-wall 6-sorter based on odd–even transposition. C(n)= n(n – 1)/2 D(n )= n Cost Delay = n 2 (n – 1)/2 = (n 3 )

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Insertion Sort and Selection Sort Fig. 7.8 Sorting network based on insertion sort or selection sort. C(n) = n(n – 1)/2 D(n ) = 2n – 3 Cost Delay = (n 3 )

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Theoretically Optimal Sorting Networks AKS sorting network (Ajtai, Komlos, Szemeredi: 1983) O(log n) depth O(n log n) size Unfortunately, AKS networks are not practical owing to large (4-digit) constant factors involved; improvements since 1983 not enough Note that even for these optimal networks, delay-cost product is suboptimal; but this is the best we can do Existing sorting networks have O(log 2 n) latency and O(n log 2 n) cost Given that log 2 n is only 20 for n = 1 000 000, the latter are more practical

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7.4 Batcher Sorting Networks One type of sorting network proposed by Batcher is based on the idea of an (m, m' )-merger and uses a technique known as even–odd merge or odd-even merge. An (m, m' )-merger is a circuit that merges two sorted sequences of lengths m and m' into a single sorted sequence of length m + m'. Let the two sorted sequences be: The odd–even merge is done by merging the even- and odd-indexed elements of the two lists separately: If we now compare–exchange the pairs of elements the resulting sequence will be completely sorted. Note that v 0, which is known to be the smallest element overall, is excluded from the final compare–exchange operations

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Batcher Sorting Networks

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Fig. 7.9 Batchers even–odd merging network for 4 + 7 inputs. (2, 3)-merger a0a0 a1a1 b0b0 b1b1 b2b2 (1, 2)-merger c0c0 d0d0 d1d1 (1, 1)(1, 2) (1, 1)

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Batchers Even-Odd Merge Sorting Batchers (m, m) even-odd merger, for m a power of 2: C(m) = 2C(m/2) + m – 1 = (m – 1) + 2(m/2 – 1) + 4(m/4 – 1) +... = m log 2 m + 1 D(m) = D(m/2) + 1 = log 2 m + 1 Cost Delay = (m log 2 m)

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Batchers Even-Odd Merge Sorting Batcher sorting networks based on the even-odd merge technique: C(n) = 2C(n/2) + (n/2)(log 2 (n/2)) + 1 n(log 2 n) 2 / 2 D(n) = D(n/2) + log 2 (n/2) + 1 = D(n/2) + log 2 n = log 2 n (log 2 n + 1)/2 Cost Delay = (n log 4 n) Fig. 7.10 The recursive structure of Batchers even– odd merge sorting network.

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Example Batchers Even-Odd 8-Sorter Fig. 7.11 Batchers even-odd merge sorting network for eight inputs.

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Bitonic-Sequence Sorter Fig. 14.2 Sorting a bitonic sequence on a linear array. Bitonic sequence: 1 3 3 4 6 6 6 2 2 1 0 0 Rises, then falls 8 7 7 6 6 6 5 4 6 8 8 9 Falls, then rises 8 9 8 7 7 6 6 6 5 4 6 8 The previous sequence, right- rotated by 2

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Batchers Bitonic Sorting Networks Fig. 7.12 The recursive structure of Batchers bitonic sorting network.

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Batchers Bitonic Sorting Networks Batchers bitonic sorting network for 16 inputs. Bitonic Sequence of inputs

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Batchers Bitonic Sorting Networks Batchers bitonic sorting network for eight inputs.

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7.5 Other Classes of Sorting Networks Fig. 7.14 Periodic balanced sorting network for eight inputs. Desirable properties: a. Regular / modular (easier VLSI layout). b. Simpler circuits via reusing the blocks c. With an extra block tolerates some faults (missed exchanges) d. With 2 extra blocks provides tolerance to any single faults (a missed or incorrect exchange) e. Multiple passes through faulty network (graceful degradation) f. Single-block design becomes fault-tolerant by using an extra stage

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Shearsort-Based Sorting Networks (1) Fig. 7.15 Design of an 8-sorter based on shearsort on 2 4 mesh.

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Shearsort-Based Sorting Networks (2) Fig. 7.16 Design of an 8-sorter based on shearsort on 2 4 mesh. Some of the same advantages as periodic balanced sorting networks

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7.6 Selection Networks Direct design may yield simpler/faster selection networks Deriving an (8, 3)-selector from Batchers even-odd merge 8-sorter.

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Categories of Selection Networks Unfortunately we know even less about selection networks than we do about sorting networks. One can define three selection problems [Knut81]: I.Select the k smallest values; present in sorted order II.Select kth smallest value III. Select the k smallest values; present in any order Circuit and time complexity: (I) hardest, (III) easiest Classifiers: Selectors that separate the smaller half of values from the larger half Smaller 4 values Larger 4 values 8 inputs8-Classifier

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Type-III Selection Networks Figure 7.17 A type III (8, 4)-selector.8-Classifier

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