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CMOS Blocks for On-Chip TF Tests Rashad Ramzan, Jerzy Dabrowski Linköping University Dept. of Electrical Engineering SE-581 83 Linköping, Sweden.

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Presentation on theme: "CMOS Blocks for On-Chip TF Tests Rashad Ramzan, Jerzy Dabrowski Linköping University Dept. of Electrical Engineering SE-581 83 Linköping, Sweden."— Presentation transcript:

1 CMOS Blocks for On-Chip TF Tests Rashad Ramzan, Jerzy Dabrowski Linköping University Dept. of Electrical Engineering SE Linköping, Sweden

2 2 June 22-25, 2005 MIXDES, Krakow, Poland Presentation Organization Motivation RF-BIST Block Diagram Defect Types Defect/Fault Propagation in RF Path Generation of Stimulus and RF Path Sensitization Test Blocks: Test Attenuator (TA) and Multiplexer (TMUX) Simulation Results Conclusions

3 3 June 22-25, 2005 MIXDES, Krakow, Poland Motivation Complete one Chip CMOS Transceivers are in market now. Like TIs BRF6300 single-chip solution for mobile terminals supporting Bluetooth Specification v2.0 How to Test Complete one Chip Radio Transceiver On Chip Digital Tests are quite mature. Digital part can be tested with out packaging the die. What about RF Testing? Its the bottleneck.

4 4 June 22-25, 2005 MIXDES, Krakow, Poland Motivation How RF is tested: RF testing before packaging: Testing Cost may approach the cost of chip. Before Packaging: Special Automatic Test Equipment. Special probing requirement, high frequency effects, Special Pad/Jig requirement etc -> More time Consuming After the packaging: Package has to be thrown away with faulty chip. And RF package is usually more costly than the chip itself. Possible Solution: Defect-oriented BiST for RF front-ends

5 5 June 22-25, 2005 MIXDES, Krakow, Poland Loopback test setup for IC RF transceiver front-end BiST by reconfiguration Sharing on-chip resources BB processor serves as TPG and response analyzer Sensitive blocks are not affected – only TA and TMUX added Tuning TA for sensitization Different tests possible Smaller loop enhances testability (DAC & ADC) But not all TRxs are well suited for loopback RF transceiver chip with BiST Tests supported: SER, EVM, FFT (for IP3), ….

6 6 June 22-25, 2005 MIXDES, Krakow, Poland Spot defects classification

7 7 June 22-25, 2005 MIXDES, Krakow, Poland Spot defects modeling by hierarchical mapping Layout R Sh RORO Circuit Chip/System M1M1 in VpVp out M2M2 R2R2 R1R1 R3R3 Open in poly Short defect Poor contact LNA LO Impairments in specs

8 8 June 22-25, 2005 MIXDES, Krakow, Poland Spot defects in CMOS M1M1 in V dd out M2M2 Br 2 Br 1 Br 3 Br 4 Br 5 M3M3 Br 6 Sh 1 Sh 2 Sh 3 Sh 4 Sh 5 Sh 6 Br 7 Narrow band LNA /0.35um /1800 MHz Noise figure Gain Noise figure Gain Fault simulation for LNA (NF 0 =3.4dB, G 0 =18.3dB) Short faults Break faults Gain and NF impairments against fault strength R br /R S or R S /R Sh Single faults are assumed Spot defects are the main yield limitation in CMOS

9 9 June 22-25, 2005 MIXDES, Krakow, Poland Spot defects (NF, G and IP3) Noise Figure Conversion Gain IP3 Impairments in gain and NF for break faults for CMOS Gilbert mixer (NF 0 =10.8dB, G 0 = 7.2dB) The corresponding impairments in IP3 (IP3 0 =7.8dBm) Less regular vs fault strength Likely to mask themselves …

10 10 June 22-25, 2005 MIXDES, Krakow, Poland Fault propagation in RF signal path LNA LO LPF IP3 test less useful for typical spot defects G Rx = G LNA G Mixer G Other Receiver front-end Also parametric faults resulting in NF, G or IP3 impairments are addressed

11 11 June 22-25, 2005 MIXDES, Krakow, Poland IP3 as test response If both IP3 1 and G 1 degraded the fault tends to mask, easier to detect with EVM (or SER) Resistive break at MOST drain introduces imbalance mostly IP3 affected, gain less R1R1 M1M1 M2M2 VbVb V out R2R2 V in IP3 is a complementary test for selected faults

12 12 June 22-25, 2005 MIXDES, Krakow, Poland Generation of stimulus at BB & Sensitization QPSK modulated BB data AWGN or Tone interferer LPFDAC Constellation with tone interferer (splitting effect) Constellation with AWGN When tuning with the interferer, TA can be fixed LO Decision boundaries must be approached by the constella- tion points in any case

13 13 June 22-25, 2005 MIXDES, Krakow, Poland Generation of stimulus at BB & Sensitization QPSK modulated BB data AWGN or Tone interferer LPFDAC Constellation with tone interferer and contribution of inherent noise Constellation with AWGN When tuning with the interferer, TA can be fixed LO

14 14 June 22-25, 2005 MIXDES, Krakow, Poland QPSK constellation BER (Bit Error Rate) & EVM (Error Vector Magnitude) EVM vs receiver NF for QPSK system sksk zkzk 2 Sin/Nref = 20dB 20dB 17dB 18.7dB

15 15 June 22-25, 2005 MIXDES, Krakow, Poland Test attenuator design If SNR is low then SNR out SNR in irrespective large NF Very large ! LNA 50 Antenna input Digital control Sin Sout NF TA = Power Loss But we can keep SNR under control

16 16 June 22-25, 2005 MIXDES, Krakow, Poland Implementation in CMOS for Wi-Fi/Bluetooth En Input D0 D1 D2 Output D3 D4 D5 Gnd TA can be disabled in normal operation mode (all MOST off) O.35 m AMS MS/RF process Layout (80 x 60) m Area < 10% of LNA area (capacitors 10pF) En D3-5 D0-2 Out In

17 17 June 22-25, 2005 MIXDES, Krakow, Poland Attenuator performance Relatively low reflection coefficient Also good linearity: IIP3 +20 dBm S11 = 2.4GHz Variable wide band attenuator, little impact of parasitics, 2 dB steps in 3 sub-ranges TA power gain TA impedance matching

18 18 June 22-25, 2005 MIXDES, Krakow, Poland 2:1 Multiplexer Design TMUX connects LNA and Mixer in Normal mode and TA and MUX in Test Mode

19 19 June 22-25, 2005 MIXDES, Krakow, Poland Test Results RF Frontend with and without Test Blocks Total Noise Figure of Frontend Total Gain of Frontend

20 20 June 22-25, 2005 MIXDES, Krakow, Poland Conclusions On-Chip Test blocks facilitate the BiST but increase chip area and tend to degrade the performance. Good models of circuits and faults supported by statistical data are needed. Sensitizing the test path very useful but not always possible. Nonstandard test stimuli and signatures very useful (invention needed). Careful DfT in initial design phase can mitigate performance degradation of RF chip.

21 21 June 22-25, 2005 MIXDES, Krakow, Poland Thank You Very much for Patience! Questions??


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