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Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

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Presentation on theme: "Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005."— Presentation transcript:

1 Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005

2 M. Al-Mosawy2 Summery - 1 Three different Adiabatic Logic families (ECRL, 2N- 2N2P and CPAL) were investigated A single inverter, a chain of four and eight inverters from each family were built and simulated to investigate the power consumption and compare it with the similar ones built in the Conventional CMOS logic The chains were connected to a load of 0.1pF to have them all driving a same load An 8-Bit Brent Kung Adder was built in two logic styles; Conventional CMOS and Complementary Pass- Transistor Adiabatic Logic (CPAL)

3 April 27, 2005M. Al-Mosawy3 Summery - 2 The power consumption for each adder style was compared with the other A voltage supply of 1.2 v was used for all of the simulations and one more voltage supply (2.5 v) was used to run a second simulation for the adders Five different frequencies (15.625 MHz, 31.25 MHz, 62.5 MHz, 125 MHz and 250 MHz) were used for each simulation and the power consumption for each run was recorded and compared among the others

4 April 27, 2005M. Al-Mosawy4 Inverters - 1

5 April 27, 2005M. Al-Mosawy5 Inverters - 2

6 April 27, 2005M. Al-Mosawy6 Single Inverters Power Compression

7 April 27, 2005M. Al-Mosawy7 Chain of Four Inverters Power Compression

8 April 27, 2005M. Al-Mosawy8 Chain of Eight Inverters Power Compression The Chain of four inverters shown in previous slide is extended to be of eight inverters The clocks of the 1 st four inverters were fed to next four inverter in the same sequence (PHI1 to inverter 5, PHI2 to Inverter 6 and so on)

9 April 27, 2005M. Al-Mosawy9 8-bit Brent Kung Adder CMOS Style All input bits including Cin were connected to clocks so that they all go high in the same time and then come low all together

10 April 27, 2005M. Al-Mosawy10 8-bit Brent Kung Adder Adiabatic Style (CPAL) The inputs and their complements (Bar) were used and so for Cin The adder consists of six stages Four clocks were used (PHI1, PHI2, PHI1Bar and PHI2Bar) and the PHI1 And PHI2 were used for stage five and six The outputs come also in Out and OutBar

11 April 27, 2005M. Al-Mosawy11 The Power Consumption Comparison Between the Two Adders As the frequency increases, the power consumption slightly increases for the CPAL B-K adder comparing with the the increasing of a similar Conv. CMOS B-K Adder

12 April 27, 2005M. Al-Mosawy12 Conclusion 1 – Power Saving and Consumption of Single Inverters Power Saving Power Consumption

13 April 27, 2005M. Al-Mosawy13 Conclusion 2 – Power Saving and Consumption of Chain of 4 Inv. Power Saving Power Consumption

14 April 27, 2005M. Al-Mosawy14 Conclusion 3 – Power Saving and Consumption of Chain of 8 Inv. Power Consumption Power Saving

15 April 27, 2005M. Al-Mosawy15 Conclusion 4 – Power Saving and Consumption of B-K Adder Power Saving Power Consumption


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