Presentation is loading. Please wait.

Presentation is loading. Please wait.

A Flow Graph Technique for DFT Controller Modification Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram Riahi*, Fabrizio Lombardi*, Zainalabedin Navabi.

Similar presentations


Presentation on theme: "A Flow Graph Technique for DFT Controller Modification Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram Riahi*, Fabrizio Lombardi*, Zainalabedin Navabi."— Presentation transcript:

1 A Flow Graph Technique for DFT Controller Modification Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram Riahi*, Fabrizio Lombardi*, Zainalabedin Navabi Electrical and Computer Engineering, University of Tehran, Iran *ECE Department, Northeastern University, USA

2 Agenda Motivation, Objectives and Contributions Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

3 Agenda Motivation, Objectives and Contributions Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

4 Motivation and Objectives Test generation at the gate-level produces high-quality tests But in the case of large systems It is computationally expensive Motivation We propose a DFT algorithm to Reducing test generation time Reducing test application time Objectives

5 Our Contributions Realize and utilize existing path of the datapath by changing controller Previous work Increase the testability of an RTL module Use datapath as search space to find test paths But, we Increase testability; decrease test application time. Use the CDFG as search space to find test paths

6 Advantages of Our Algorithm Reduce test application time Using pre-computed test vector Reducing test generation effort Very small area overhead on controller No timing penalty of critical path (in the datapath)

7 Agenda Motivation, Objectives and Contributions Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

8 CDFG and Synthesis *1+2*3 *4+5 *6*7 *8 -9 abcd e f g z1 z2 z3 z4 z5 z6 z7 z8 y 5 3 CLK1 CLK2 CLK3 CLK4 CLK5 *1 The behavioral description of a circuit is usually provided using a hardware description language like VHDL. This description is compiled into a control/data flow graph (CDFG), which is a directed graph with operation vertices, data variable arcs, conditions, and loops. CDFG can be used for extracting control and data information during synthesis steps Scheduling Binding

9 Datapath & Controller

10 Test-Path in the Datapath z1, z4, z6, y z3, z7, z8 z2, z5 a b3 f g 5c ed Group 1 * * +- Group 2 Group 3 Group 4 Module Under Test (Pre-computed test vectors are available)

11 A Problem!!! This Test-Path is not supported by the controller!!! Using the CDFG as the search space, a controller supported Test-Path can be found

12 Agenda Motivation, Objectives and Contributions Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

13 Test-Path in CDFG The role of a controller is to map the CDFG of a circuit to its datapath. Consequently, All paths in a CDFG exist in the datapath of a circuit. However, there may be additional paths in a datapath that do not necessarily exist in a CDFG that the datapath is generated from.

14 Test-Path in CDFG controller-supported paths: paths in a datapath can be activated for passing data by the existing controller of the circuit. controller-unsupported paths : paths of the datapath that are not specified by the CDFG and are not activated by the existing controller To recognize and thus utilize these paths, changes may be needed in the circuits controller.

15 Faulty Operator in the CDFG If a module in the RTL is faulty, all operators in its group of the CDFG became faulty. This means that multiple faults appear in the CDFG. To avoid this scenario, only one operator is considered as a victim operator as faulty and the CDFG is pruned by deleting all other operators in the group as well as all their connecting nodes.

16 Victim A victim is an existing/new operator that 1. Receives its inputs from outside of its group and 2. Propagates its output to outside of its group, and 3. Pruned CDFG corresponding to the victim operator must have at least a primary output of the original CDFG.

17 Victims Group i a b c Victim Group i a b c c b a Victim Group i a b c c b a

18 Test Time Reduction Test application time can be reduced using two techniques Finding best victim when a victim has alternatives Removing unnecessary states in the Pruned CDFG (Explained in the example)

19 Agenda Motivation, Objectives and Contributions Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

20 Group 1 z1, z4, z6, y z3, z7, z8 z2, z5 a b3 f g 5c ed Group 1 * * +- Group 2Group 3 Group 4

21 Group 1 Victim *1+2*3 *4+5 *6*7 *8 -9 abcd e f g z1 z2 z3 z4 z5 z6 z7 z8 y 5 3 CLK1 CLK2 CLK3 CLK4 CLK5 z1 and y are mapped in the same register in the Datapath *1 Victim Group 1

22 Group1 Testing *1 ab CLK1 *1 y Pruned CDFG Just one clock cycle is enough to apply each pre-computed test vector to this RTL module

23 Group2 z1, z4, z6, y z3, z7, z8 z2, z5 a b3 f g 5c ed Group 1 * * +- Group 2 Group 3 Group 4

24 z7 z8 Group 2 Victim *1+2*3 *4+5 *6*7 *8 -9 abcd e f g z1 z2 z3 z4 z6 z5 y 5 3 z1 and z6 are mapped in the same register in the Datapath z3 and z8 are mapped in the same register in the Datapath Victim *v S1 S2S3S5S4 Group 2

25 Group 2 Testing *1 *3 -9 ab f g y CLK1 CLK5 S1 S2S3S5S4 Just two clock cycles are enough to apply each pre-computed test vector to this RTL module

26 Group4 z1, z4, z6, y z3, z7, z8 z2, z5 a b3 f g 5c ed Group 1 * * +- Group 2 Group 3 Group 4

27 Group4 Victim *1+2*3 *4+5 *6*7 *8 -9 abcd e f g z1 z2 z3 z4 z6 z5 z7 z8 y 5 3 CLK1 CLK2 CLK3 CLK4 CLK5 *1 Victim Group 4 Group 4 has only one member, so it is a compulsory victim operator. The DFG for this victim is the same as the original CDFG. This CDFG can be reduced by the elimination of clocks 2, 3 and 4.

28 Reducing the CDFG Graph of Group 4 *1+2*3 *4+5 *6*7 *8 -9 abcd e f g z1 z2 z3 z4 z6 z5 z7 z8 y 5 3 *1 The utilization of shared registers of the datapath are the basic principle for reducing the test application time. Using a bipartite graph the obtained CDFG is reduced

29 Group 4 Testing *1 *3 -9 ab f g y CLK1 CLK5 S1 S2S3S5S4 Just two clock cycles are enough to apply each pre-computed test vector to this RTL module

30 Agenda Motivation, Objectives and Contributions Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

31

32 Questions!


Download ppt "A Flow Graph Technique for DFT Controller Modification Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram Riahi*, Fabrizio Lombardi*, Zainalabedin Navabi."

Similar presentations


Ads by Google