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MIP-based Detailed Placer for Mixed-size Circuits Shuai Li, Cheng-Kok Koh ECE, Purdue University {li263, chengkok}@purdue.edu

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Outline Motivation Incomplete SCP model Experimental results Summary

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Background Placement minimize total wirelength, estimated with half parameter wirelength (HPWL) routability-driven placement avoid routing congestion Global placement optimized approximate locations; Detailed placement after legalization; rearrange cells to reduce HPWL

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Detailed placement cell swap/move technique FastPlace-DP, global and vertical cell swap/move congestion-aware FastPlace-DP, routability-driven placers sliding window technique partition the whole chip into overlapping windows moving cells locally in windows has less perturbance to routability enumeration approach; solution space O(n!) for n -cell window; windows with no more than 6 cells alternative approaches to optimize larger windows branch-and-bound technique, cell matching technique, etc.

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MIP approach for detailed placement Mixed Integer Programming (MIP) approach placement of each window is formulated into an MIP problem: linear objective function & linear constraints; integer variables mature mathematical techniques for solving MIP problems a branch-and-bound tree is built during solution, whose size is dependent on the number of integer variables MIP models for detailed placement the S model, the RQ model, the SCP model the single-cell-placement (SCP) model over 10 times more efficient than the other MIP models

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MIP-based detailed placer Parallelized MIP-based detailed placer IBM Version 2 benchmark circuits Initial placement results generated with enumeration approach; 1.684% further reduction in HPWL; 0.827% and 1.707% further reduction in routed wirelength and via count, respectively. Apply it to recent mixed-size circuits? benchmark circuits in ISPD11, DAC12, ICCAD12 routability-driven contests

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IBM Version 2 DAC12 Challenges with recent mixed-size circuits DAC12 benchmark circuits n.c. number of cells o.r. occupation rate, the rate that sites are occupied by cells 400 extracted 10-cell windows n.s. average number of sites n.v. average number of integer variables in SCP model;

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Our contribution DAC12 benchmark circuits over 10 times more cells over 2 times more sites in sliding windows over 10 times increase in solution time of each window Incomplete SCP model ignore a portion of integer variables in SCP model great reduction in solution time without much degradation in solution quality MIP-based detailed placer for DAC12 benchmark circuits

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Outline Motivation Incomplete SCP model Experimental results Summary

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Problem description Objective: minimize HPWL Constraints: 1. no cell overlap; 2. each cell is placed legally, i.e. cell c occupies exactly w c consecutive sites in one row R : set of rows Q : set of columns C : set of cells w c : width of cell c N : set of nets

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Single-cell-placement variables single-cell-placement (SCP) variable: whether the kth pattern to place single cell c is chosen or not Single-cell-placement patterns and corresponding vectors e.g. cell 1 in the 3X7 window; |R|(|Q|-w c +1)= 18 variables in all

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SCP Model (llx n, lly n, urx n, ury n ): bounding box of net n ; (x c, y c ): centroid of cell c; p crq : whether cell c occupies the site at row r and column q definition of bounding box site occupation cell centroid and site occupation variables derived from SCP variables one pattern for each cell

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Incomplete SCP Model definition of bounding box site occupation cell centroid and site occupation variables derived from SCP variables one pattern for each cell skipping patterns

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Incomplete SCP Model (contd) o c = 1, when skip =3, only the 1 st, 4 th, 7 th, 10 th, 13 th, 16 th are kept e.g. cell 1 in the 3X7 window; |R|(|Q|-w c +1)= 18 variables in all

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Incomplete SCP Model (contd) Guideline to set skip exact locations in the solution may be non-optimal guarantee different orders of placing cells are still in the solution space skip=1 for compact windows; larger skip for sparse windows with low occupation rate (ocp_rt) and more empty sites

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Two incomplete SCP models Number of variables for cell c in SCP model: v c is close to summation of cell width, the same as in the SCP model of placing the same cells in a compact window SCP_ES model, set skip based on number of empty sites In compact windows, skip =1 In sparse windows with ocp_rt close to 0.0, v c is close to |C|, the same as in the SCP model of placing the same number of uniform-width cells SCP_OR model, set skip based on occupation rate

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Outline Motivation Incomplete SCP model Experimental results Summary

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Effect of incomplete models tolerance time 40s, 60s, 800s for 8-cell, 10-cell, 12-cell windows SCP_OR model, a good compromise of the SCP model fewer than a half integer variables (n.v. ) over 6 times faster (t(s)), within 10% degradation in HPWL reduction (red.) SCP_ES model 1/5 variables, 100 times faster with 40% degradation used in our parallelized MIP-based detailed placer Enumeration approach (ENUM) few windows are optimized with the same tolerance time

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Results on DAC12 benchmark circuits MIP-based detailed placer 2-row and 4-row windows with no more than 10 cells windows are scanned for 3 times Initial placement results generated by different placers Ripple NTUPlace4 Two commercial routers to generate detailed routing solutions Router A, Router B existing translator from Bookshelf files to LEF/DEF files W.-H. Liu et al. Case study for placement solutions in ISPD11 and DAC12 routability-driven placement contests. In Proc. ISPD, pages 114–119, 2013.

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Effects on Ripples results INIT: initial results generated with congestion-aware FastPlace-DP MIP: results after MIP-based detailed placer Router A WL(e7): routed wirelength VIA(e7): via count VIO: number of detailed routing violations T(m): routing run-time OF: overflows in global routing

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Effects on NTUPlace4s results INIT: initial results generated with cell matching technique MIP: results after MIP-based detailed placer Router A WL(e7): routed wirelength VIA(e7): via count VIO: number of detailed routing violations T(m): routing run-time OF: overflows in global routing

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Effects on Ripples results INIT: initial results generated with congestion-aware FastPlace-DP MIP: results after MIP-based detailed placer Router B

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Effects on NTUPlace4s results INIT: initial results generated with cell matching technique MIP: results after MIP-based detailed placer Router B

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Outline Motivation Incomplete SCP model Experimental results Summary

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MIP approach for detailed placement optimize larger sliding windows to further reduce wirelength Application in recent large-scale benchmark circuits Over 10 times more cells; Lower occupation rate leading to significant increase in the solution time of each window Incomplete SCP model ignore variables to significantly decrease solution time; Despite degradation in solution quality, still effective reduction in wirelength is achieved without perturbance of routability

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Thank you!

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Large-scale mixed-size circuits #cellt(s)opt ibm01 8-cell0.82100% 10-cell1.9399.7% 12-cell5.8696.4% s16 8-cell9.294.4% 10-cell19.690.7% 12-cell113.376.8% Over 300 randomly extracted windows for each size ibm01: IBM Version 2 benchmark tolerance time 40s s16: DAC12 benchmark tolerance time 40s, 60s, 800s for 8-cell, 10-cell, 12-cell windows, respectively longer average solution time t(s) lower optimization rate opt Larger solution space for windows with more empty sites 1-row window with n cells and m empty sites More integer variables in MIP results in the increase of solution time

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