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JERARQUÍA DE MEMORIA MEMORIA VIRTUAL SEMANA NO.15 SEMESTRE 2011-2 PROF. EUGENIO DUQUE PÉREZ PROF. GUSTAVO PATIÑO

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Presentation on theme: "JERARQUÍA DE MEMORIA MEMORIA VIRTUAL SEMANA NO.15 SEMESTRE 2011-2 PROF. EUGENIO DUQUE PÉREZ PROF. GUSTAVO PATIÑO"— Presentation transcript:

1 JERARQUÍA DE MEMORIA MEMORIA VIRTUAL SEMANA NO.15 SEMESTRE PROF. EUGENIO DUQUE PÉREZ PROF. GUSTAVO PATIÑO 1 Arquitectura de Computadores Departamento de Ingeniería Electrónica Facultad de Ingeniería

2 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Virtual Memory 2 The main memory can act as a cache for the secondary storage, usually implemented with magnetic disks. This technique is called Virtual Memory. There are two major motivations for virtual memory: to allow efficient and safe sharing of memory among multiple programs and to remove the programming burdens of a small, limited amount of main memory.

3 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Virtual Memory (…cont) 3 Main memory needs to contain only the active portions of the many programs, just as a cache contains only the active portion of one program. This allows us to efficiently share the processor as well as the main memory. Virtual memory implements the translation of a programs address space to physical addresses. This translations enforces protection of a programs address space from other programs.

4 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Virtual Memory (…cont) 4 Virtual memory manages the two levels of the memory hierarchy represented by main memory (sometimes called physical memory to distinguish it from virtual memory) and secondary storage. Although the concepts at work in virtual memory and in caches are the same, their differing historical roots have led to the use of different terminlogy.

5 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Terminology 5 Page : A block in the virtual memory. Page fault : A virtual memory miss. A page fault will take millions of cycles to process. This enormous miss penalty, dominated by the time to get the first word for typical page sizes, leads to several key decisions in designing virtual memory systems. Memory mapping (or address translation) : With virtual memory, the CPU produces a virtual address which is translated by a combination of HW and SW to a physical address, which in turn can be used to access main memory. Analogy : Virtual Address can be seen like book title Physical address like location of that book in the library.

6 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Mapeo de Memoria 6

7 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Mapeo de Memoria (…cont) 7

8 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Mapeo de Memoria (…cont) 8 El número de bits en el page offset determina el tamaño de la página. El número de páginas direccionables con la dirección virtual no necesita corresponder con el número de páginas direccionables con la dirección física. Tener un número mayor de páginas virtuales, que el número de páginas físicas, es la base de la ilusión de una cantidad esencialmente ilimitada de memoria virtual.

9 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Decisiones claves para el diseño de memoria virtual 9

10 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Placing a page and finding it again 10 If we allow a virtual page to be mapped to any physical page (fully associative placement), the operating system can then choose to replace any page it wants when a page faults occurs. Problems : it would be necessary a full search.

11 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Placing a page and finding it again (…cont) 11 In virtual memory, we locate pages by using a full table that indexes the memory. This structure is called a page table. A page table is indexed with the page number from the virtual address and contains the corresponding physical page number.

12 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Placing a page and finding it again (…cont) 12 Each program has its own page table, which maps the virtual address space of that program to main memory. To indicate the location of the page table in memory, the HW includes a register that points to the start of the page table. Page Table Register.

13 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería The Page Table 13

14 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería The page table (…cont) 14 Because the page table contains a mapping for every possible virtual page, no tags are required. In cache terminology, the index, which is used to access the page table, consists of the full block address, which is the virtual page number.

15 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería What happen with every program ? 15 The page table, together with the program counter and the registers, specifies the state of a program. If we want to allow another program to use the CPU, we must save this state. Later, after restoring this state, the program can continue execution. This state is often refer as a process. The process is considered active when it is in possesion of the CPU; otherwise, it is considered inactive. Rather than save the entire page table, the operating system symply loads the page table register to point to the page table of the process it wants to make active.

16 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Making Address Translation Fast : The TLB 16 Since the page tables are stored in main memory, every memory access by a program can take at least twice as long: one memory access to obtain the physical address and a second access to get the data. The key to improving access performance is to rely on locality of reference to the page table. When a translation for a virtual page number is used, it will probably be needed again in the near future because the references to the words on that page have both temporal and spatial locality.

17 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería The TLB 17 Accordinly, modern machines include a special cache that keeps track of recently used translations. This special address translation cache is traditionally referred to as a Translation Lookaside Buffer (TLB). The TLB is a cache that holds only page table mappings. Thus each tag entry in the TLB holds a portion of the virtual page number, and each data entry of the TLB holds a physical page number.

18 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería The TLB (…cont) 18

19 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Integrating Virtual Memory, TLBs and Caches 19

20 Departamento de Ing. Electrónica. Arquitectura de Computadores Facultad de Ingeniería Ejemplo del procesamiento de una condición de lectura o escritura en el procesador DECStation


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