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Daniel OrozcoDaniel Orozco Guang GaoGuang Gao

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Mapping FDTD to Many-Cores Daniel Orozco2

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Mapping FDTD to Many-Cores Daniel Orozco3 FDTD = Finite Difference Time Domain FDTD simulates the propagation of electromagnetic waves through materials.

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Mapping FDTD to Many-Cores Daniel Orozco4

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8 Read Create New Overwrite

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Mapping FDTD to Many-Cores Daniel Orozco9 Memory Loads Per Element Computed: 9 Memory Loads Per Element Computed: 1.44

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Mapping FDTD to Many-Cores Daniel Orozco10

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Mapping FDTD to Many-Cores Daniel Orozco11

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Mapping FDTD to Many-Cores Daniel Orozco12

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Mapping FDTD to Many-Cores Daniel Orozco13

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Mapping FDTD to Many-Cores Daniel Orozco14

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Mapping FDTD to Many-Cores Daniel Orozco15

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Logical View Tile shape Mapping FDTD to Many-Cores Daniel Orozco16 No Lost Computations Tiles are fully parallel. No lost computations. Very simple programming.

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Logical View Mapping FDTD to Many-Cores Daniel Orozco17 Tiles are fully parallel. No lost computations. Useful to understand the problem.

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Mapping FDTD to Many-Cores Daniel Orozco18 Reuse = 40 Reuse = 5

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Mapping FDTD to Many-Cores Daniel Orozco19 No Tiling Simple Tiling Skewed Tiling Overlapped Tiling Split Tiling Triangle Tiling Parametric Tiling p = 0.5 Diamond Tiling Not Embarrassingly Parallel Developed at CAPSL The Fine Print: Values are for a tile size of 100. Reuse values change with the size of the tile. Results apply to 1 Dimensional Stencil Computation with dependencies similar to those of the examples.

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Mapping FDTD to Many-Cores Daniel Orozco20 No Tiling Triangle Size = 16 Triangle Size = 64 Diamond Size = 64 Diamond Size = 16 The Fine Print: Simulated Speedup Results for FDTD 1D running on Cyclops-64 using FAST simulator. Problem size varies for each test, and was selected as big as possible. Only the computation time was measured. Problem data located in DRAM. Tiling done manually. GCC 3.4, -O3 used.

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Mapping FDTD to Many-Cores Daniel Orozco21 Diamond Size = N Parametric Size = N Low Reuse High Reuse Low Reuse High Reuse

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