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Measurements on pre-production wafers at Udine Presented by M. Cobal on behalf of the Udine group Pixel Week December 2001.

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Presentation on theme: "Measurements on pre-production wafers at Udine Presented by M. Cobal on behalf of the Udine group Pixel Week December 2001."— Presentation transcript:

1 Measurements on pre-production wafers at Udine Presented by M. Cobal on behalf of the Udine group Pixel Week December 2001

2 Measured Wafers CiS Tesla A A A A31-12

3 Outline Tiles and diodes with guard ring –IV measurements –CV measurements –tile conformity SCs and MCs yield Visual inspection –ID marking correctness –visual inspection –mask alignment

4 IV measurements This time, taken with 2-side chuck Temperature corrections applied

5 Diode position n side #17 #16

6 IV meas. on diode #17 (CiS)

7 IV meas. on diode #17 (Tesla)

8 Quality Control Parameters Tile conformity criteria: –V bd (tile)> V op (diode) V op V op -50)<2 V op =max(V dep +50,150) Need to measure V dep

9 Capacitance offset

10 CV results

11

12 - Measurements lie within 65 V < V dep < 100 V - Procedure specs demanded: 30 V < V dep < 120 V - For all wafers : V dep <100 V V op = max(V dep +50,150) = 150 V Determination of V dep and V op

13 C dep is between ( ) pF for CIS (Tesla) Determined as: C dep =C(V dep )-C offset C offset of order of pF (for positive polarity) lies within k cm conformity range is 2-5 k cm Determination of C dep and

14 Tile results (CiS) Results in agreement with CIS 2 wafers with 2 good tiles 2 wafers with 3 good tiles wafer with Slope (Tile 1) = 3.58

15 SC and MC yield (CiS) SCs: 6 x 4= 24 5 are bad (Vbd<150) 79% are good MCs: 4 x 4 = 16 1 is bad (Vbd<150) 94% are good

16 Disagreement for 1 Wafer out of 4: Wafer A31-12 Slope(Tile 2): Our measureTesla Tile results (Tesla)

17 SCs: 6 x 4=24 1 is bad (Vbd<150) 96% are good MCs: 4 x 4=16 4 are bad (Vbd<150) 75% are good SC and MC yield (Tesla)

18 2- and 3-good-tile wafers: –TILES: all 4 pads marked. –SCs: only 1 of the 2 pads marked (lower one). –All markings are correct. Scratch pad marking (CIS)

19 2 and 3 good tiles wafers –TILES: only 2 out of 4 pads marked. –SCs: only 1 of the 2 pads marked (lower one). –All markings are correct. Scratch pad marking (Tesla)

20 Visual Inspection (CiS) n-side: Tile 2, small scratch (6 pixels) #16, extended scratch (superficial) n-side: Tile 1, one pixel defective Tile 2, Tile 3, three pixels defective #22, extended scratch (superficial) MC13, one pixel larger

21 Visual Inspection (Tesla) A31-02 p-side: #17, small scratch #12, small scratch A31-08 n-side: #19, extended scratch p-side: bad end of the three top structures

22 Scratch

23 Mask alignment vernier Goal: Measure 2 mm misalignment Use: Nikon Optiphot X

24 Mask alignment (CiS) Good contrast For vertical vernier, 4 vs 5 bars

25 Mask alignment (CiS) Out of specifications: Wafer : n-side, left pad, 4 th hor. right pad, 4 th hor. p-side, right pad, 4 th hor. Wafer : n-side, right pad, 4 th hor. p-side, right pad, 4 th hor. Wafer : n-side, left pad, 4 th hor. right pad, 4 th hor. p-side, right pad, 4 th hor.

26 Quite bad contrast for all the vernier All 3rd vernier are missing All the 4th vernier are badly printed Mask alignment (Tesla)

27 Out of specifications: Wafer A31-02: p-side, right pad, 1 st vert. Wafer A31-07: p-side, right pad, 1 st vert. Wafer A31-12: p-side, left pad, 4 th vert.

28 Database The new wafers (both CiS and Tesla) have been already inserted in the database IV measurements will be added very soon For CV measurements, needs to understand better


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