Presentation on theme: "Augusto Panecatl Technical Information and Customer Support"— Presentation transcript:
1 Augusto Panecatl Technical Information and Customer Support ARM Cortex M0+®Augusto PanecatlTechnical Information and Customer Support
2 Cortex-M0 processorsCortex-M series processors have been specifically developed for the microcontroller industry where the need for fast, highly deterministic, interrupt management is coupled with the desire for extremely low gate count and lowest possible power consumption.La serie de procesadores Cortex-M se han desarrollado principalmente para el dominio microcontrolador donde la necesidad de rápida altamente determinista, la gestión, la interrupción es, junto con el deseo de recuento extremadamente bajo puerta y el más bajo consumo de energía posible.Applications include:MicrocontrollersMixed signal devicesSmart sensorsAutomotive body electronics and airbags
3 Cortex-M0 processors Energy efficiency Run at lower MHz or during shorter activity periodsArchitected support for sleep modesSmaller codeHigh density instruction setAchieve more per byte than 8/16-bit devices
4 Cortex-M0 processors Ease of use Global standard across multiple vendorsCode compatibilityHigh Performance
5 Cortex-M0 ProcessorsCortex-M family processors are all binary upwards compatible, enabling software reuse and a seamless progression from one Cortex-M processor to another.
6 Cortex M ScalabilityCode fully upward compatible with Kinetis K Cortex-M4
7 ARM Cortex-M0+ : The True 8-bit Replacement The smallest, lowest-power ARM processor on the marketProcessor consumption as low as 9μA/MHz*Outstanding results of 1.77 CoreMark/MHzI/O low-power improvements with single cycle access to critical peripherals (GPIO …)Relocatable vector table allows for dynamic exception handlers by moving the vector table into RAMMicro trace buffer brings fast debug advantages of trace to low-end MCUs
8 Cortex-M0+ 32-bit RISC processor 2-stage pipeline von Neumann architectureARMv6-M architecture16-bit Thumb instruction set with Thumb-2 technology.Load-Store Architecture56 InstructionsBecause there are several generations of ARM processors, the architectures of these processors are also divided into different version.Where each version defines a programmers model, instruction set, exception mechanism.
9 Simplified Block Diagram NVIC The NVIC is an embedded interrupt controller that supports low latency interruptprocessing. Up to 32 Interrupt signals. Priority features, tail-chaining and External NMI.The system timer SysTick, is a 24-bit count-down timer. Use this as a Real TimeOperating System (RTOS) tick timer or as a simple counterWIC can detect an interrupt and wake the processor from deep sleep mode.The WIC is not programmable, and does not have any registers or user interface.When the WIC is enabled and the processor enters deep sleep mode, the power management unitin the system can power down most of the Cortex-M0+ processor.MPU –Debug System: It allows to handle breakpoint and watchpoints.Debug Access Port . JTAG or Serial Wire .(5 & 2 lines)
10 Nested Vectored Interrupt Controller (NVIC) En profundidad: Nested Vectored controlador de interrupciones (CNTV)El CNTV es una parte integral de todos los procesadores Cortex-M y ofrece excelentes capacidades de manejo de interrupciones de los transformadores. En los procesadores Cortex-M0, Cortex-M0 + y Cortex-M1, el apoyo NVIC hasta 32 interrupciones (IRQ), una interrupción no enmascarable (NMI) y varias excepciones del sistema. Los procesadores Cortex-M3 y Cortex-M4 se extienden del CIV para soportar hasta 240 IRQ, NMI 1 y otras excepciones del sistema.
11 Programmers modelThread mode Executes application software. The processor enters Thread mode when itcomes out of reset.Handler mode Handles exceptions. The processor returns to Thread mode when it hasfinished all exception processingUnprivileged The software:• has limited access to system registers using the MSR and MRSinstructions, and cannot use the CPS instruction to mask interrupts• cannot access the system timer, NVIC, or system control block• might have restricted access to memory or peripherals.Unprivileged software executes at the unprivileged level.Privileged The software can use all the instructions and has access to all resources.Privileged software executes at the privileged level.StacksThe processor uses a full descending stack.
12 Memory model 4GB of memory address space Code Region SRAM Region Peripheral RegionRAM RegionDevice RegionInternal Private Peripheral BusDivided into a number of regions. Each region has its recommended usage.Support only aligned transfersExternal Device .- 2* 512MB does not allow program execution. Used for general data storage.External RAM MB allows program executionPeripheral. Not execution allowed. Connected to AHB bus or APB.SRAM.- 512MBCode.- Vector Table, code and data.
13 ARM Cortex-M0+ Processor: Low Power by Design Dedicated features built-in the processor:WFI & WFE instructions: set core into SLEEP and Wait-For-Event/InterruptSleep-on-Exit: automatic SLEEP after interrupt executionFew cycles to switch between run and sleepDEEP SLEEP for longer sleep period:CPU and NVIC unpoweredWIC monitors wake-up sourcesStatic processor leakage in nWKINETIS L implementation:Asynchronous WIC (AWIC)Multiple WU sources: periph/LV/NMIAdditionnal LLWU for low leakage wake upISR exitActive ModeISRSleep ModeSleep ModeSLEEPONEXIT bit setWFI or WFE
14 Ultra-low Power ModesExpands beyond typical run, sleep and deep sleep modes with power options designed to maximize battery life in varying applicationsModeDefinitionRunMCU can be run at full speed. Supports Compute Operation clocking option where bus and system clock are disabled for lowest power core processing and energy-saving peripherals with an alternate asynchronous clock source are operational.VLP Run(VLPR)MCU maximum frequency is restricted to 4MHz core/platform and 1 MHz bus/flash clock. Supports Compute Operation clocking option. LVD protection is off and flash programming is disallowed.WaitAllows all peripherals to function, while CPU goes to sleep reducing power consumption. No Compute Operation clocking option.VLP Wait(VLPW)Similar to VLP Run, with CPU in sleep to further reduce power. No Compute Operation clocking option.StopMCU is in static state with LVD protection on. Energy-saving peripherals are operational with Asynchronous DMA (ADMA) feature that can wake-up DMA to perform transfer and return to current mode when complete. AWIC detects wake-up source for CPU. Lowest power mode with option to keep PLL active.VLP Stop(VLPS)MCU is in static state with LVD protection off. Energy-saving peripherals are operational with ADMA feature. AWIC detects wake-up source for CPU.LL Stop(LLS)MCU is in low leakage state retention power mode. LLWU detects wake-up source for CPU including LPTMR, RTC, TSI, CMP, and select pin interrupts. Fast <4.3us wake-up.VLL Stop 3 (VLLS3)MCU is placed in a low leakage mode powering down most internal logic. All system RAM contents are retained and I/O states held. LLWU controls wake-up source for CPU similar to LLS mode.VLL Stop 1(VLLS1)Similar to VLLS3 with no RAM or register file retention.VLL Stop 0(VLLS0)Pin wakeup supported. LPTMR, RTC, TSI and CMP wake-up supported with external clock. No RAM or register file retention. Optional POR brown-out detection circuitry.RUNSLEEPDEEP SLEEP
15 Crystal Oscillator (low & high range) Kinetis L Series: Master Block DiagramSystemClock ManagementEnergy ManagementUnique IDARM Cortex-M0+ CoreUltra-low power48MHz bus freq.Debug(SWD)COPLPO(1KHz)Crystal Oscillator (low & high range)LS Osc(32KHz)Voltage RegulatorRSTFlash8-256KRAM1-32KDMA 4-chFLLPLLULP Osc(4MHz)Power On ResetLow Voltage DetectorPeripheral BusAnalog InterfacesTimersCommunicationConnectivityI/O PortsADC (SAR w/ DMA)12/16-bit, up to 16chPIT2ch, 32bit16b LPTPM6ch x1, 2ch x 2UART x2LPUARTx1IISx1USB FS/LS TransceiverUp to 80 GPIO(4 High Dive)w/ 25 interruptSPI x 2USB Controller12-bit DACHSCMPSRTCTemp. CompensatedLPTMRTSI x 16chRST/InputI2C x 2V RegulatorHMIOperation in:RunWaitStop/VLPSVLLS3VLLS1VLLS0Segment LCD51x8/55x4Packages: 16QFN, 20WLCSP, 24QFN, 32LQFP, 32QFN, 35WLCSP, 48LQFP, 48QFN, 64LQFP, 80LQFP, 100LQFP, 121MBGA