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R. Ernst, TU Braunschweig 1 Embedded System Modeling Part 1 R. Ernst TU Braunschweig, Germany.

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Presentation on theme: "R. Ernst, TU Braunschweig 1 Embedded System Modeling Part 1 R. Ernst TU Braunschweig, Germany."— Presentation transcript:

1 R. Ernst, TU Braunschweig 1 Embedded System Modeling Part 1 R. Ernst TU Braunschweig, Germany

2 R. Ernst, TU Braunschweig 2 Lecture Overview 1Introduction and motivation 2Application modeling 3Target architecture modeling Part 1 Part 2

3 R. Ernst, TU Braunschweig 3 Lecture Overview 1Introduction and motivation 2 Application modeling 3 Target architecture modeling

4 R. Ernst, TU Braunschweig 4 Embedded Systems Embedded System microcomputer system embedded in a technical system examples

5 R. Ernst, TU Braunschweig 5 Embedded Systems - Trends Trend 1: higher system integration –integration of complete programmable subsystems on a single IC - Systems-on-Chip (SOC) –programmable platforms examples: network processors, multi-media platforms, automotive platforms

6 R. Ernst, TU Braunschweig 6 Automotive Platform - Example MPC 555 Flash RAM (448 KB) SRAM (26 KB) burst interface U-bus Power PC (RCPU) system control E-bus bus interface bus interface Inter Module Bus CAN bus interface (2) CAN bus interface (2) serial multi- channel module serial multi- channel module peripheral channels (PWM...) bus interface bus interface ADC (2x16) ADC (2x16) time processing unit (2) time processing unit (2) programmable processors weakly prog. co-processors reused components (IP) memories interface& control

7 R. Ernst, TU Braunschweig 7 MPC 555 IC consists for the most part of IP and reused components source: Motorola and Microprocessor Report, April 20, 98

8 R. Ernst, TU Braunschweig 8 Platform component types Another example: Philips Nexperia TM platform (Source: Th. Claasen, DAC 2000) SDRAM TM-core D$ I$ TriMedia CPU DEVICE I/P BLOCK DVP System Silicon PI BUS MMI DVP MEMORY BUS DEVICE I/P BLOCK core D$ I$ MIPS CPU DEVICE I/P BLOCK PI BUS TriMedia TM MIPS TM programmable processors OS + API + custom SW weakly programmable co-processors configurable IP components memories communication components

9 R. Ernst, TU Braunschweig 9 Embedded System - Trends - 2 Trend 2: networked systems ubiquitous computing, telecom, automotive, avionics, space,... subsystem integration Image source: Siemens service integration service integration

10 R. Ernst, TU Braunschweig 10 Embedded System Design Constraints many non functional constraints influence design goals and architectures –tight cost margins –hard time constraints –power consumption (mobile systems) –safety including EMI –size, weight,... reduced and overlapping design cycles

11 R. Ernst, TU Braunschweig 11 Embedded architectures are heterogeneous different processing element types – processors, weakly programmable coprocessors, IP components different interconnection networks and communication protocols different memory types different scheduling and synchronization strategies M CoP M M PDSP M P

12 R. Ernst, TU Braunschweig 12 Managing HW architecture complexity development of application programmer interfaces (API) to hide complexity from application programmer and improve portability specialized RTOS to control resource sharing and interfaces complex multi-level HW/SW architecture

13 R. Ernst, TU Braunschweig 13 Software architecture example Chip Bus core RTOS I/OInt Bus- CTRL timer drivers RTOS-APIs application periphery cache mem private shared hardware software architecture application layered software architecture with API embedded SW is heterogeneous ce 1 pe 1 API

14 R. Ernst, TU Braunschweig 14 RTOS SW- library (drivers etc.) API, middle ware, RTOS (e.g. VxWorks) SW architecture - 2 B3 B2 B1 B4 process languages, e.g. C, SystemC, VHDL P4 P3 P2 P1 shared memory application run-time system P4 P3P2 P1

15 R. Ernst, TU Braunschweig 15 ES implementation challenges integration –design process integration –heterogeneous component and language integration (VSIA, Accellera) design space exploration and optimization verification

16 R. Ernst, TU Braunschweig 16 Lecture Overview 1Introduction and motivation 2Application modeling 3Target architecture modeling

17 R. Ernst, TU Braunschweig 17 2 Application modeling use of different modeling languages in a single system –languages/semantics established in application domain: flow graphs, FSM,... –domain specific optimizations required signal flow graph transformations, FSM transformations,... –investment in language environments single design language unlikely Simulink subsystem 2 input language 2 subsystem 3 subsystem 1 IP UML

18 R. Ernst, TU Braunschweig 18 Application & Architecture implementation language architecture layer application articulation point subsystem 2 Simulink input language 2 subsystem 3 1 IP UML application development application layer Part 1: application models Part 2: architecture models implementation

19 R. Ernst, TU Braunschweig 19 Embedded System Modeling Principles standard embedded system model –networks of communicating processes (P1, P2) –processes locally sequential P1P2

20 R. Ernst, TU Braunschweig 20 Sequential processes sequential process languages (Host language) –programming languages C, C++, Java, assembly language,... –hardware description languages VDHL processes, SystemC processes P1P2

21 R. Ernst, TU Braunschweig 21 Sequential process modeling unbuffered control and acyclic data flow graphs {j = i * 2 + 1; g [i] = a [j] * p [i]; if (g [j] > max_val) g [j] = max_val;} for (i==0; i <= n/2; i++) g j max_val i * [] g p a * > = i basic block no branch except at end process control flow

22 R. Ernst, TU Braunschweig 22 Sequential process modeling - 2 basic block (BB) represented by data flow graph (DFG) –nodes are elementary operations –edges are variables/signals –acyclic graph –signals not buffered operations activated (ready) if all signals/variables available (AND) all output signals available after operation execution basic model for compilers and HW synthesis tools –operation scheduling (but: RT and logic synthesis assume single cycle) –allocation of operations, variables, busses

23 R. Ernst, TU Braunschweig 23 Sequential process modeling - 3 process control flow represented by control flow graph –nodes are basic blocks –edges represent control branches –signals not buffered basic blocks activated if flow arrives on one input edge (OR) one output branch activated after BB execution global model for compilers and HW synthesis tools –in HW synthesis often combined in single graph (CDFG)

24 R. Ernst, TU Braunschweig 24 Process communication communication is part of the process coordination language P1P2 shared variable communication P4 P3 P2 P1 shared memory a = b + c; g = a * c; message passing communication P4 P3P2 P1 send (a); receive (a);

25 R. Ernst, TU Braunschweig 25 2 Application modeling Important application models –Kahn graphs –concurrent FSM and synchronous/reactive systems –asynchronous processes –systems with periodic process activation –others (e.g. Petri nets) different coordination semantic Models of computation

26 R. Ernst, TU Braunschweig 26 Kahn process networks communicating processes with directed flow communication: token stream between two processes process: operations on tokens P1 stream P2 stream

27 R. Ernst, TU Braunschweig 27 Kahn process networks special class of process networks communication via FIFO with unbounded capacity process: –destructive read (consumption) at process start –non-destructive write (production) at process end –blocking read - process only executed if data available –non-blocking write P1 FIFO P2 FIFO

28 R. Ernst, TU Braunschweig 28 Kahn process networks - 2 monotonous process –a process is monotonous if F(x 1 x 2... x n x n+1 ) F(x 1 x 2... x n ) i.e., the output string grows with the input string monotonous Kahn process networks are independent of the order of process executions –excellent for design space exploration –buffering supports pipelining –process order / scheduling can be optimized for processor cost minimization FIFO memory minimization - token are often data arrays (e.g. frames) timing constraints - often periodic I/O data token (signal proc.) –minimum cycle defines maximum schedule length

29 R. Ernst, TU Braunschweig 29 Data flow process networks data flow process networks are Kahn process networks with firing rules –conditions for process execution: number and type of tokens (AND) –output tokens per process execution examples of data flow process networks –SDF - processes consume / produce fixed number of tokens (Lee/Messerschmitt) –cyclo static DF - processes cycle through a fixed token prod/cons (Lauwereins) –boolean DF - token cons/prod depends on boolean control input (Buck/Lee) commercial tools COSSAP, SPW, DSP Station,...

30 R. Ernst, TU Braunschweig 30 Example: Modem (Lee[86]) optimization for minimal program size (single appearance) (16A)(16B)(2C)IJKLM(2N)PFDOEGH

31 R. Ernst, TU Braunschweig 31 FSMs Finite state machines (FSM) –Moore FSM –Mealy FSM

32 R. Ernst, TU Braunschweig 32 Moore FSM M = (S, I, O, –S state set –I input set –O output set – I x S S transition function – S output function s1/o1s2/o2 i ijij Moore FSM graphMoore FSM structure OI mem S S´

33 R. Ernst, TU Braunschweig 33 Mealy FSM M = (S, I, O, –S state set –I input set –O output set – I x S S transition function – I x S output function s1s2 i i /o 2 i j /o 1 Mealy FSM graph Mealy FSM structure OI mem S S´

34 R. Ernst, TU Braunschweig 34 FSM semantics synchronous switching networks –state transition at every clock cycle (RTL) general FSM –FSM transits upon new input value or input event –abstracts from target architecture clocking implementation not constrained HW implementation 1 to n clock cycles SW implementationm processor instructions

35 R. Ernst, TU Braunschweig 35 Concurrent FSM complex system functions described as concurrent FSM –easier to understand –usually lower implementation cost –required for multiprocessor and networked systems FSM 1 FSM 2

36 R. Ernst, TU Braunschweig 36 Concurrent FSMs example - traffic lights F2 ry1 g y2 F1 A1 A2 A1 S = {r, y1, y2, g} E = {F1, F2} F1: vehicle approaches light 1 F2: vehicle approaches light 2 wait for 5s and F1 and A2.r wait for 2s wait for 20s wait for 5s wait for 5s and F2 and not F1 and A1.r ry1 g y2 A2 wait for 2s wait for 20s wait for 5s

37 R. Ernst, TU Braunschweig 37 traffic light implementation SW : n instruction cycles + signal communication HW: 1 to n clock cycles + signal communication FSM transition time implementation dependent non-deterministic behavior

38 R. Ernst, TU Braunschweig 38 reachability for asynchronous FSM must extend behavior to exclude illegal states –semaphore, monitor,... Concurrent FSM cooperation r y1 rr y1 g rr g y2 r r r y2 r y1 y1 y1 r g r y1 % ! !... A1 A2 F1 F1, F2 F2 non deterministic behavior non deterministic behavior: behavior is not only dependant on FSM input and state illegal behavior

39 R. Ernst, TU Braunschweig 39 Behavior extension using monitor AM idle A1ack A1.req A1.rA2.r A2.req A1 AM.A2ack A2 rreq gy2 wait for 5s and F1 and AM.idle wait for 2s wait for 20s wait for 5s y1 rreq gy2 wait for 5s and F2 and AM.idle wait for 2s wait for 20s wait for 5s y1 AM.A1ack A2ack AM

40 R. Ernst, TU Braunschweig 40 Synchronous FSM state transition in t deterministic behavior –simplifies simulation and verification –implementation t implementation strongly constrained must introduce global synchronization or guarantee target architecture timing

41 R. Ernst, TU Braunschweig 41 reachability for synchronous FSM r y1 rr y1 g rr g y2 r r r y2 % A1 A2 F1 F2 and not F1 Traffic light with synchronous FSM

42 R. Ernst, TU Braunschweig 42 Synchronous reactive systems FSM processes communicate via events with t ev process is activated by any input event (OR) process reacts instantaneously output data are immediately available to all other processes timing is introduced as time events P1 event P2 P3 P5 event after t 1 : event event P4 event

43 R. Ernst, TU Braunschweig 43 Synchronous reactive systems - 2 properties relevant to implementation –better control of system response times than in system with buffering –exact time events + instantaneous signaling and execution defines total order of events and process executions (synchronous FSMs) system determinate (if processes are determinate) –total order of process execution and exact timing cause design space limitation impact depends on target architecture and system requirements high importance for computation intensive tasks and tight timing requirements

44 R. Ernst, TU Braunschweig 44 Synchronous reactive systems - 3 hierarchical extensions for complex systems language examples: ESTEREL, STATECHARTs (UML),... reg zero lapoff on chime time B B C B D H run D disp [in(run.on)] [in(] A A stopwatch stopwatch example (STATECHART)

45 R. Ernst, TU Braunschweig 45 Asynchronous communicating processes example: SDL (System description language) –locally controlled processes with buffered communication –processes control buffer function –complex semantics with non-determinism –used in telecommunication –example: Telelogic Tau

46 R. Ernst, TU Braunschweig 46 Periodically activated processes example SIMULINK (The MathWorks) processes B1,..., B4; input output ports (i1, o1, o2) activation period ts communication using shared variables –destructive write, non destructive read potential data loss B1 ts =1 B4 ts=4 B3 ts =3 B2 ts =2 i1o2 o1

47 R. Ernst, TU Braunschweig 47 Other semantics Petri nets –rich class of related semantics CFSM (VCC) environment: continuous time models

48 R. Ernst, TU Braunschweig 48 Combining models of computation co-simulation approach compositional approach Simulink subsystem 2 input language 2 subsystem 3 subsystem 1 IP UML

49 R. Ernst, TU Braunschweig 49 optimization Co-simulation approach individual implementation with local optimization and low-level communication synthesis subsystem1 (lang 1) optimization subsystem 2 (lang 2) optimization subsystem n (lang n)... integration network integration network - shallow integration –co-simulation backplane –common communication protocol for co-synthesis co-design & validation 1 co-design & validation 1 co-design & validation 2 co-design & validation 2 co-design & validation n co-design & validation n environment (lang x)

50 R. Ernst, TU Braunschweig 50 Co-Simulation Strategies one simulator with foreign language interface to other models –examples: VHDL simulator centralized event scheduling and timing –simulator backbone (timing architecture dependent - part 2) decentralized, hierarchical event scheduling –example: PTOLEMY

51 R. Ernst, TU Braunschweig 51 PTOLEMY co-simulation hierarchy of domains communicating through event horizons block porthole initialize () receive data () send data () block porthole event horizon scheduler domain (subsystem 1) domain n event horizon event schedule synchronization

52 R. Ernst, TU Braunschweig 52 Integration network limitations semantics exploitation in implementation very limited global constraints example: timing constraints across subsystems bus interface process network bus interface t max memory system optimization: buffer optimization under changing system states IP HW and SW modules shared (heterogeneous) target platform and predefined RTOS often many suppliers particular problem: no details known

53 R. Ernst, TU Braunschweig 53 Compositional approaches PCC and Stateflow PTOLEMY II and Cocentric SPI

54 R. Ernst, TU Braunschweig 54 Process coordination calculus - PCC process network with 2 process types (Grötker et al.) –data driven processes: may be activated if sufficient token (SDF) –event driven processes: activated at any input event (FSM) –event and stream edges SDF process SDF process FSM process SDF process event (queues) stream execution order dependent behavior –order of data process execution determines event process behavior –event arrival times influence data process behavior

55 R. Ernst, TU Braunschweig 55 PCC - 2 approach: use additional scheduling constraints to control network behavior design space limitation commercial language with 2 process types: Stateflow (SIMULINK)

56 R. Ernst, TU Braunschweig 56 *charts [Girault, Lee, Lee, 97] hierarchical process network (PTOLEMY II) refinement of processes –single model per process node –different models across hierarchy –rules for embedding process nodes with different semantics example: requires termination of minimum cycle in DF - process nodes –hierarchy order: FSM - X 1 - FSM - X 2 - FSM -..., where X i : SDF, HDF, SR, DE (discrete event)

57 R. Ernst, TU Braunschweig 57 game off game on coin/blueLt exit/redLt error/flashTilt,redLt FSM coin ready go stop time blueLt yellowLt greenLt redLt flashLt *charts - example SR time ready go stop yellowLt greenLt error exit wait stop end wait go idle FSM timeout/errorend/greenLt ready ^ ¬ timeout /start stop/error stop/exit timeout/error time ready go stop error exit greenLt start player 1 player 2 time ready stop end start go time yellowLt end error exit greenLt start wait idle start/yellowLt go timeout /end time start go end yellowLt FSM timetimeout FSM SR FSM SDF add delay constant compare time timeout SDF

58 R. Ernst, TU Braunschweig 58 Hierachical process networks - 2 commercial tool: CoCentric System Studio (Synopsys) –hierachical combination of data flow process network and synchronous reactive model –many additional constructs, such as weak and strong process termination, gated processes,...

59 R. Ernst, TU Braunschweig 59 PCC and *charts both models can be used as a general representation –for simulation (executable nodes) –for optimization low-level coordination language used both require adherence to predefined model(s) of computation –legacy code, 3 rd party SW, partially documented system parts?

60 R. Ernst, TU Braunschweig 60 Single model with intervals - SPI SPI - System Property Intervals ( abstract model with intervals [Ziegenbein et al.] process communication via channels –FIFO buffers (C) destructive read, non-destructive write –registers (R) destructive write, non-destructive read system properties annotated as intervals –communication, timing, constraints covering systems with conditional or unknown behavior virtual processes and channels to model coordination

61 R. Ernst, TU Braunschweig 61 Example - remote motor control try_receive (message) from PI; if adress(message) = MyAdress then value = decode(message); send (value) to P3; end if; global parameter P3: motor control loop P1: bus interface control D I1: bus signal O1: error signal I3: sensor signal O3: motor control signal P2: bus message processing SDF 16 t 1 t1t1 t3t3 < t lat,

62 R. Ernst, TU Braunschweig 62 Remote motor control - SPI model P bus P1P1 C 11 C 12 C 13 C7C7 C8C8 C9C9 C 10 C6C6 P time C1C1 C 14 P2P2 P error C2C2 P 31 P motor C [0,1] 16 [0,16] [0,1] 1 1 d init = 1 d init = 15 1 d init = 16 d init = 1 LC = [ t 1, t 1 ] 1 C 15 P sensor 1 1 C 16 d init = 1 LC = [ t 3, t 3 ] P 32 P 33 1 C 18 1 C C d init = 1 SDF periodic activation with deadline = e.o. period domain coupling

63 R. Ernst, TU Braunschweig 63 Part 1 - Conclusion process networks are standard in embedded systems application languages different models of computation support exploitation of subsystem properties multi-language designs with reuse are becoming standard languages combination with co-simulational or compositional approach compositional approach more complex but exploits global system properties for implementation (research)

64 R. Ernst, TU Braunschweig 64 Literature Overview –G. DeMicheli, R. Ernst, W. Wolf. Readings in Hardware/Software Co-design. Morgan Kaufmann Publishers, Collection of papers on modeling, simulation and implementation. Compiler –A.V. Aho, R. Sethi, J.D. Ulmann. Compilers: Principles, Techniques and Tools. Addison-Wesley, Reading, 88. –S. Muchnick. Advanced Compiler Design Implementation. Morgan Kaufmann Publishers, 97. Synthesis –G. DeMicheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 94.

65 R. Ernst, TU Braunschweig 65 Literature - 2 Models of Computation –E. A. Lee, Th. M. Parks: Dataflow Process Networks, Proceedings of the IEEE, Vol. 83, No. 5, pp , May –N. Halbwachs: Synchronous Programming of Reactive Systems, Kluwer Academic Publishers, –D. Harel: The STATEMATE Semantics of StateCharts, ACM Transactions on Software Engineering and Methodology, 5(4), pp , October –ITU-T: Recommendation Z.100. CCITT specification and description language SDL, –A. Girault, B. Lee, E. A. Lee: A Preliminary Study of Hierarchical Finite State Machines with Multiple Concurrency Models, Technical Report UCB/ERL M97/57, –T. Grötker, R. Schoenen, H.Meyr: PCC: A Modeling Technique for Mixed Control/Data Flow Systems, Proceedings of ED&TC ´97, pp , 1997.

66 R. Ernst, TU Braunschweig 66 Literature - 3 Models of Computation - contd –S. A. Edwards. Languages for Digital Embedded Systems. Kluwer Academic Publishers, –SPI papers:

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