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ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 10.

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Presentation on theme: "ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 10."— Presentation transcript:

1 ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 10

2 Topics ADuC7026 External Memory Interface Implementation Demultipexing Bus Timing Bus cycle timing modification Wait states and more Assessing timing compatibility

3 Basic System Bus Operation Address Unidirectional from CPU Data Bidirectional Control /RS or /RD – output from CPU Indicates a read operation in progress /WS or /WR – output from CPU Indicates a write operation in progress /WAIT or /READY – input to CPU Used by external device to signal that it is not able to complete transfer yet (not present on ADuC7026)

4 ADuC7026 Bus Operation The ADuC7026 external memory interface consists of 16-bit multiplexed address/data bus (AD15:0) High address bit for 8-bit operation (A16) 128kB regions require 17 bits of address Read and write strobes (/RS, /WS) Memory select signals (/MS3:0) Internal decodes of upper 15 bits of address Byte enables (/BHE, /BLE) Used when memory interface is operating at 16-bit width Demultiplexing control signal (AE) Used to control logic that holds address valid to memory system There is no WAIT/READY signal

5 Basic Read Cycle at Bus Level

6 Basic Write Cycle at Bus Level

7 ADuC7026 Demultiplexing Multiplexed Signal Timing Read Cycle Dealing with a multiplexed bus Demultiplexing by the device Demultiplexing logic to create an address bus Implementation Devices Connections AE timing

8 16-Bit Memory System

9 SRAM Timing Compatibility In order to properly read and write the device, we need to ensure that the processor-to-memory interface is compatible with the memory device. This is accomplished by analyzing the timing for all relevant parameters, and ensuring that the operation can be completed successfully. We will work through the read cycle analysis for the ADuC

10 Assessing Timing Compatibility Need to know whether CPU could operate with the t AA for given device. We designate a CPU characteristic t AVDV, which is the delay from When the address becomes valid at the CPU Until the data must be driven back to CPU This establishes an upper bound on t AA t AA < t AVDV Read cycle parameters Read cycle timing control

11 Basic Read Cycle at Bus Level

12 Read Cycle Controls

13 System Timing Compatibility Need to account for all delays in a system to assess timing compatibility. Consider this system.system Analyze the read timing with regard to: t AA – address access time t ACS – chip enable to valid data t OE – output enable to valid data t DF – output hold/float time

14 t AA – address access time

15 t ACS – chip enable to valid data

16 t OE – output enable to valid data

17 t DF – output hold/float time

18 ADuC7026 External Memory Interface Configuration The external memory interface supports four independently configured memory regions, each of which is 128kB in size. In order to use the external memory interface, we need to Configure the required pins (GPxCON) Enable the external interface (XMCFG[0] = 1) Region enable and bus width (XMxCON) Configure region for the desired bus timing (XMxPAR)

19 ADuC7026 XMxCON The XMxCON registers configure the bus width and enable the interface for the respective memory region. Only D[1:0] are used. XM0CON 0x x1001FFFF XM1CON 0x x2001FFFF XM2CON 0x x3001FFFF XM3CON 0x x4001FFFF

20 ADuC7026 XMxPAR The XMxPAR MMR configures the bus timing for a region 0x70FF at reset [14:12] – AE extend [9] – implements bus turn-around [8] – provides additional hold time [7:4],[3:0] – extend write/read strobes Write cycle timing control Read cycle timing control

21 System Timing Compatibility Consider again the system.system Analyzing write cycle timing.write cycle SRAM write characteristics t WC t AS, t AW, t CW t WR t WDS, t WDH Write cycle controls

22 Timing Wrap-Up Device characteristics are just part of the total timing analysis picture Line/device capacitive loading and driver slew rates Transmission line effects and parasitic reactances Impedance mismatch and reflections Skew and physical/electrical trace length mismatch Signal integrity Ensuring that signals are correct in spite of all of the above issues and mutual coupling effects

23 Wrapping Up Have a great Spring Break! Complete Pre-Quiz #5 by the start of class on Monday, April 9 th Homework #5 will be due on Wednesday, April 11 th Reading for next week (interrupts and exceptions) Textbook chapter 10 ADuC ARM

24 Basic Read Cycle

25 Basic Write Cycle

26 Read Cycle Parameters

27 Write Cycle Parameters

28 Read Cycle Controls

29 Write Cycle Controls

30 16-Bit Memory System

31 Ref


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