8 ARM Platform (1) Arbiter Only one bus master has access to the bus Each bus master requests control of the bus Arbiter decides which has the highest priority and issues a grant signal
9 Decoder The system decoder is used to decode the address bus Generate select lines to each of the system bus slaves or masters ARM Platform (2)
10 ARM Platform (3) Default slave The default slave is used to respond to transfer that are made to undefined regions of memory map
11 ARM Platform (4) AMBA Bus (Master to slave multiplexer) The master to slave multiplexor is used to connect all of the system bus masters to the bus slaves, using the current HMASTER number to select the bus master outputs to use.
12 ARM Platform (5) AMBA Bus (Slave to master multiplexer) The slave to master multiplexor is used to connect the read data and response signals of the system bus slaves to the bus masters, using the current HSELx outputs to select the bus slave outputs to use.
13 ARM Platform (6) ARM920T Wrapper The ARM920T AHB wrapper interfaces between the ARM920T core and AHB bus.
14 ARM Platform (7) ARM920T Wrapper ARM920TWrapSM Converts the ASB accesses form the core into pseudo-AHB accesses Main state machine Address generation ARM920TWrapMaster Converts the pseudo-AHB accesses form ARM920TSM into true-AHB accesses Error control (Holding, Error report to ARM920T core) ARM920TWrapSlave Converts incoming AHB accesses into ASB accesses to the ARM920T core
15 Direct Memory Access Controller Peripheral-to-Memory, Memory-to-Peripheral, Peripheral-to-Peripheral, and Memory-to-Memory transactions. ARM Platform (8)
16 ( 2004 1 ~ 2004 12 ) 123456789101112 1 ARM platform test ( APB, Peripheral, memory controller, EBI) 2 DSP platform test (BIU, decoder, memory) 3 Communication Interface & DMMU 4 1 Multiprocessor Platform test 5 HW/SW partitioning block test 6 Multiprocessor platform DVB-T test 7 Multiprocessor (Arm+DSP) platform 8 Multiprocessor platform DVB-T test 2
17 1.M. Shalan and V. Mooney, "Hardware Support for Real-Time Embedded Multiprocessor System-on-a- Chip Memory Management," CODES'02, pp 79-84, May 2002Hardware Support for Real-Time Embedded Multiprocessor System-on-a- Chip Memory Management 2.Baghdadi, A.; Lyonnard, D., Zergainoh, N.-E., Jerraya, A.A. An efficient architecture model for systematic design of application-specific multiprocessor SoC DATE, 2001. pp 55 -62, March 2001 3.Gharsalli, F., Lyonnard, D., Meftali, A., Rousseau, F., Jerraya, A.A, Unifying memory and processor wrapper architecture in multiprocessor SoC design, ISSS 2002, Page(s): 26 -31, Oct, 2002 4.Christou, C.S. Fast computations on a low-cost DSP-based shared-memory multiprocessor system Electronics, Circuits and Systems, 17-20, Page(s): 189 -192. Dec. 2000 5.www.arm.comwww.arm.com 6.www.parthusceva.comwww.parthusceva.com 7.http://tima-cmp.imag.fr/Homepages/jerraya/jerraya.htmlhttp://tima-cmp.imag.fr/Homepages/jerraya/jerraya.html 8.http://www.aijisystem.com/index_korea.htm, scorpio users manualhttp://www.aijisystem.com/index_korea.htm