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EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

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Presentation on theme: "EE 587 SoC Design & Test Partha Pande School of EECS Washington State University"— Presentation transcript:

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

2 SoC Physical Design Issues Interconnect Architectures and Signal Integrity

3 Design Challenges 1. Non-scalable global wire delay 2. Moving signals across a large die within one clock cycle is not possible. 3. Current interconnection architecture- Buses are inherently non-scalable. 4. Transmission of digital signals along wires is not reliable.

4 Bus – non scalability Clock cycle depends on the parasitic and bus length Multiple bus segments More than one design iteration Converges to network

5 Bus Architectures

6 Split Bus Architecture

7 Achievable Clock Cycle in a Bus segment

8 Minimize Power Consumption Modification of interconnect architectures Incorporate parallelism (ITRS 2003 & ISSCC 2004) Decoupling of communication and processing Modular architecture Minimize use of global wires Locality in communication

9 SoC Micro architecture Trend K gates block – No global wire delay problem. Block-based hierarchical design style that uses block sizes of K gates. Single synchronous clock regions will span only a small fraction of the chip area. Different self-synchronous IPs communicate via network- oriented protocols. Structured network wiring leads to deterministic electrical parameters - reduces latency and increases bandwidth. Failures due to inherent unreliable physical medium can be addressed by introducing error correction mechanisms.

10 New design paradigm New designs – very large number of functional blocks Moving bits around efficiently Develop on-chip infrastructure to solve future inter-block communication bottlenecks Development of infrastructure IPs SoC = (SFIP + SI 2 P)

11 Silicon Back plane

12 MIPS SoC-it

13 The network-on-chip paradigm Driven by Increased levels of integration Complexity of large SoCs – New designs counting 100s of IP blocks Need for platform-based design methodologies DSM constraints (power, delay, time-to-market, etc…)

14 Decoupling of functionality from communication Dedicated infrastructure for data transport NoC infrastructure switch link NoC Features

15 Some Common Architectures (a) Mesh, (b) Folded-Torus (FT) and (c) Butterfly Fat Tree (BFT)

16 Data Transmission Packet-based communication Low memory requirement Packet switching Wormhole routing Packets are broken down into flow control units or flits which are then routed in a pipelined fashion

17 Connecting Different IP Blocks Using Tree Architecture

18 Communication Pipelining Need to constrain the delay of each stage within 15 FO4

19 Signal Integrity According to ITRS signal integrity will become a major issue in future technologies Causes for such inherent unreliability Shrinking geometries, layout dimensions Reduction in the charge used for storing bits Increased probability of transient events like: Crosstalk Ground Bounce Alpha particle hits

20 Micro network Protocol Stack

21 On Chip Signal Transmission Future global wires will function as lossy transmission lines Reduced-swing signaling Noise due to crosstalk, electromagnetic interference, and other factors will have increased impact. it will not be possible to abstract the physical layer of on-chip networks as a fully reliable, fixed-delay channel At the micro network stack layers atop the physical layer, noise is a source of local transient malfunctions.

22 Coding Schemes Low-Power Coding Reducing self-transition activity Crosstalk Avoidance Coding Reducing Coupling with adjacent lines Error Control Coding SEC, SECDED

23 Low Power Coding Reduction of self-transition activity Bus-Invert Code Data is inverted and an invert bit is sent to the decoder if the current data word differs from the previous data word in more than half the number of bits Effectiveness decreases with increase in bus width

24 Error Control Coding Linear block codes (n, k) linear block code, a data block, k bits long, is mapped onto an n bit code word, Forward Error Correction or Automatic Repeat Request Redundant wires Possibility of voltage reduction Energy efficiency is an important criterion Codec overhead

25 Worst Case Crosstalk Transition from 101 to 010 pattern or vice versa Due to Miller Capacitance worst case capacitance between adjacent wires become

26 Joint Crosstalk Avoidance and Single Error Correction Codes Reduce crosstalk as well correct errors due to other transient events Duplicate Add Parity (DAP) Dual Rail Code (DR) Boundary Shift Code (BSC) Modified Dual Rail Code (MDR) Worst case crosstalk capacitance is reduced to (1+2λ)C L

27 Duplicate-Add-Parity Code Each bit is duplicated A parity bit from one copy is computed Same as Dual Rail Code

28 Crosstalk Avoidance Double Error Correction Code (CADEC) The 32-bit flit is Hamming coded and then an overall parity is calculated All bits apart from the overall parity are duplicated The 32 bit original flit becomes 77 bits Minimum Hamming distance is 7 Worst case crosstalk capacitance is reduced to (1+2λ)CL

29 Energy Savings with Joint Codes Due to increased error resilience lower noise margins can be tolerated and hence operating voltage can be reduced Coding adds overhead in terms of extra wires and codec

30 Voltage Swing Reduction for CADEC V Word error rate The probability of word error for DAP

31 Energy Savings with CADEC

32 Communication Pipelining Inter- and Intra-switch stages Pipelined Data Transfer

33 Latency Characteristics The codes should be optimized It can be merged with existing stages No Latency penalty

34 Adaptive Supply Voltage Links Dynamic Voltage Scaling (DVS) DVS schemes dynamically adjust the processor clock frequency and supply voltage to just meet instantaneous performance requirement, making the system energy aware. communication architectures display a wide variance in their utilization depending on the communication patterns of applications adapts the links frequency and supply voltage in accordance with the instantaneous traffic bandwidth.

35 Repeater Insertion & Coding Repeater insertion reduces interconnect wire delay Increases power dissipation due large drivers CACs reduce coupling capacitance Joint repeater insertion and CAC is a promising solution to reduce power in global wires

36 Repeater Insertion & Coding Reference: A low- Power Bus Design Using Joint Repeater Insertion and Coding 130 nm

37 Repeater Insertion & Coding 45 nm

38 Reliability Crosstalk, electromigration,material ageing…. Transient failures Error control coding Crosstalk avoidance coding Power, area trade-off Permanent failures Spare switches and links Overall routing complexity Effect on system performance

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