Presentation on theme: "Washington State University"— Presentation transcript:
1Washington State University EE 587 SoC Design & TestPartha PandeSchool of EECSWashington State University
2SoC Physical Design Issues Interconnect Architectures and Signal Integrity
3Design Challenges Non-scalable global wire delay Moving signals across a large die within one clock cycle is not possible.Current interconnection architecture- Buses are inherently non-scalable.Transmission of digital signals along wires is not reliable.
4Bus – non scalabilityClock cycle depends on the parasitic and bus lengthMultiple bus segmentsMore than one design iterationConverges to network
8Minimize Power Consumption Modification of interconnect architecturesIncorporate parallelism (ITRS 2003 & ISSCC 2004)Decoupling of communication and processingModular architectureMinimize use of global wiresLocality in communication
9SoC Micro architecture Trend 50-100K gates block – No global wire delay problem.Block-based hierarchical design style that uses block sizes of K gates.Single synchronous clock regions will span only a small fraction of the chip area.Different self-synchronous IPs communicate via network-oriented protocols.Structured network wiring leads to deterministic electrical parameters - reduces latency and increases bandwidth.Failures due to inherent unreliable physical medium can be addressed by introducing error correction mechanisms.
10New design paradigmNew designs – very large number of functional blocksMoving bits around efficientlyDevelop on-chip infrastructure to solve future inter-block communication bottlenecksDevelopment of infrastructure IPsSoC = (SFIP + SI2P)
13The network-on-chip paradigm Driven byIncreased levels of integrationComplexity of large SoCsNew designs counting 100s of IP blocksNeed for platform-based design methodologiesDSM constraints (power, delay, time-to-market, etc…)
14NoC Features Decoupling of functionality from communication Dedicated infrastructure for data transportNoC infrastructureswitchlink
15Some Common Architectures (a) Mesh, (b) Folded-Torus (FT) and (c) Butterfly Fat Tree (BFT)
16Data Transmission Packet-based communication Low memory requirement Packet switchingWormhole routingPackets are broken down into flow control units or flits which are then routed in a pipelined fashion
17Connecting Different IP Blocks Using Tree Architecture
18Communication Pipelining Need to constrain the delay of each stage within 15 FO4
19Signal IntegrityAccording to ITRS signal integrity will become a major issue in future technologiesCauses for such inherent unreliabilityShrinking geometries, layout dimensionsReduction in the charge used for storing bitsIncreased probability of transient events like:CrosstalkGround BounceAlpha particle hits
21On Chip Signal Transmission Future global wires will function as lossy transmission linesReduced-swing signalingNoise due to crosstalk, electromagnetic interference, and other factors will have increased impact.it will not be possible to abstract the physical layer of on-chip networks as a fully reliable, fixed-delay channelAt the micro network stack layers atop the physical layer, noise is a source of local transient malfunctions.
22Coding Schemes Low-Power Coding Reducing self-transition activity Crosstalk Avoidance CodingReducing Coupling with adjacent linesError Control CodingSEC, SECDED
23Low Power Coding Reduction of self-transition activity Bus-Invert Code Data is inverted and an invert bit is sent to the decoder if the current data word differs from the previous data word in more than half the number of bitsEffectiveness decreases with increase in bus width
24Error Control Coding Linear block codes (n, k) linear block code, a data block, k bits long, is mapped onto an n bit code word,Forward Error Correction or Automatic Repeat RequestRedundant wiresPossibility of voltage reductionEnergy efficiency is an important criterionCodec overhead
25Worst Case Crosstalk Transition from 101 to 010 pattern or vice versa Due to Miller Capacitance worst case capacitance between adjacent wires become
26Joint Crosstalk Avoidance and Single Error Correction Codes Reduce crosstalk as well correct errors due to other transient eventsDuplicate Add Parity (DAP)Dual Rail Code (DR)Boundary Shift Code (BSC)Modified Dual Rail Code (MDR)Worst case crosstalk capacitance is reduced to (1+2λ)CL
27Duplicate-Add-Parity Code Each bit is duplicatedA parity bit from one copy is computedSame as Dual Rail Code
28Crosstalk Avoidance Double Error Correction Code (CADEC) The 32-bit flit is Hamming coded and then an overall parity is calculatedAll bits apart from the overall parity are duplicatedThe 32 bit original flit becomes 77 bitsMinimum Hamming distance is 7Worst case crosstalk capacitance is reduced to (1+2λ)CL
29Energy Savings with Joint Codes Due to increased error resilience lower noise margins can be tolerated and hence operating voltage can be reducedCoding adds overhead in terms of extra wires and codec
30Voltage Swing Reduction for CADEC The probability of word error for DAPVWord error rate
32Communication Pipelining Inter- and Intra-switch stagesPipelined Data Transfer
33Latency Characteristics The codes should be optimizedIt can be merged with existing stagesNo Latency penalty
34Adaptive Supply Voltage Links Dynamic Voltage Scaling (DVS)DVS schemes dynamically adjust the processor clock frequency and supply voltage to just meet instantaneous performance requirement, making the system energy aware.communication architectures display a wide variance in their utilization depending on the communication patterns of applicationsadapts the link’s frequency and supply voltage in accordance with the instantaneous traffic bandwidth.
35Repeater Insertion & Coding Repeater insertion reduces interconnect wire delayIncreases power dissipation due large driversCACs reduce coupling capacitanceJoint repeater insertion and CAC is a promising solution to reduce power in global wires
36Repeater Insertion & Coding Reference: A low-Power Bus Design Using Joint Repeater Insertion and Coding130 nm
38Reliability Crosstalk, electromigration,material ageing…. Transient failuresError control codingCrosstalk avoidance codingPower, area trade-offPermanent failuresSpare switches and linksOverall routing complexityEffect on system performance