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Best of Both Worlds: A Bus-Enhanced Network on-Chip (BENoC) Ran Manevich, Isask har (Zigi) Walter, Israel Cidon, and Avinoam Kolodny Technion – Israel.

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Presentation on theme: "Best of Both Worlds: A Bus-Enhanced Network on-Chip (BENoC) Ran Manevich, Isask har (Zigi) Walter, Israel Cidon, and Avinoam Kolodny Technion – Israel."— Presentation transcript:

1 Best of Both Worlds: A Bus-Enhanced Network on-Chip (BENoC) Ran Manevich, Isask har (Zigi) Walter, Israel Cidon, and Avinoam Kolodny Technion – Israel Institute of Technology May, 2009

2 2 Network on-Chip : the Good News Interconnect for SoCs, CMPs and FPGAs Multi-hop, packet-based communication Efficient resource sharing Scalable performance and efficiency in Power Area Design productivity System Bus

3 3 Network on-Chip : the Bad News Increased and hard-to-predict latency due to multi-hop and sharing Time critical signals Broadcast? multicast? No easy solutions Slow (10s of cycles) I wish I had a bus at hand ….

4 4 Solution: Bus-Enhanced NoC (BENoC) Bus re-introduced as a NoC add-on Use NoC for data Optimized for high bandwidth Use bus for short meta-data Low bandwidth, low latency Broadcast, multicast Overhead should be justified! R RRRR R R RRR R R RR R R R RR R R R R R RR RR R R R R Module

5 5 In-band support of time critical communication; and: In-band Multicast/Broadcast Complex router implementation Suffer from multi-hop latency Existing Bus-NoC hybrids Form a topological hierarchy Typically bus used for local communication Related Work Module R R RR R RRR R RR R RR R RR R

6 6 BENoC Services Fast unicast and multicast signaling CMP cache example Anycast Find resources that fulfills certain conditions E.g., Looking for an idling DSP; or Where are the 5 closest multipliers? Convergecast Efficient collection of feedback back to the initiator Barrier synchronization, …

7 7 Additional BENoC Applications NoC control Router configuration E.g., routing table configuration Adapt NoC routing for load balancing Fault discovery and recovery System control Power management Resource load balancing Debug

8 8 Outline Introduction MetaBus architecture MetaBus latency and energy analysis CMP cache use case

9 9 Conventional System Buses Figure is copied from Amba Specifications Rev 2.0 - http://www.arm.com/products/solutions/AMBA_Spec.html Bandwidth optimized Poor scalability Not suitable for tasks in BENoC

10 10 MetaBus Design Requirements Low area, low power Low bandwidth Low latency Simple Versatile Scalable Multicast and broadcast support Acknowledgement R R R R RR R RRRR RRRR R Module MetaBus

11 11 MetaBus Architecture Many possible implementations Example: tree topology with distributed arbitration Module #1 Module #2 Module #3 Module #4 Module #5 Module #6 Module #7 Module #8 Module #9 Bus Station Root Bus Station

12 12 Module #1 Module #2 Module #3 Module #4 Module #5 Module #6 Module #7 Module #8 Module #9 Bus Station Root Bus Station Data Path Data to root Data to receivers

13 13 Module #1 Module #2 Module #3 Module #4 Module #5 Module #6 Module #7 Module #8 Module #9 Bus Station Root Bus Station Address wordpropagates to the root Data word 1 Data word 2 propagates to the modules Example: Broadcast of Two Words

14 14 Module #1 Module #2 Module #3 Bus Station Root Bus Station Distributed Arbitration Mechanism Bus Request Bus Grant

15 15 Module #1 Module #2 Module #3 Module #4 Module #5 Module #6 Module #7 Module #8 Module #9 Bus Station 3 Bus Station 4 Bus Station 5 Bus Station 2 Root Bus Station 1 Address wordpropagates to the root Data word 1 propagates to the modules Masking Saves Power Mask1 Mask2 Mask3 Mask4 Mask5 Mask1Mask2 Mask3Mask4Mask5 Unicast from Module#3 to Module#5 10 101 1010110101

16 16 (Binary) Bus Station

17 17 MetaBus Floorplan – An Example 64 modules balanced binary MetaBus

18 18 Outline Introduction MetaBus architecture MetaBus Latency and energy analysis CMP cache use case

19 19 Analysis Highlights 1/4 NoC Broadcast+Unicast Energy/Transaction:

20 20 Analysis Highlights 2/4 MetaBus Broadcast and Unicast Energy/Transaction:

21 21 Analysis Highlights 3/4 NoC unicast and broadcast latency:

22 22 Analysis Highlights 4/4 MetaBus unicast and broadcast latency:

23 23 Results - Energy Consumption Energy consumption for a 3 data words broadcast and unicast transactions Bus and NoC unicast and broadcast energy per transaction 10X10 mm chip 64 modules mesh 1GHz NoC clock Speed optimized bus @0.18um

24 24 Results - Latencies 3 data words broadcast and unicast transactions latencies in system with a frequency and a speed optimized MetaBus. Figure 9: Bus and NoC broadcast latencies 10X10 mm chip 64 modules mesh 1GHz NoC clock Speed optimized bus @0.18um

25 25 Outline Introduction MetaBus architecture MetaBus Latency and energy analysis CMP cache use case

26 26 Dynamic Non-Uniform Cache Access Split large cache into independent smaller banks Non uniform cache access time (NUCA) Cache lines are moved to shorten access time Dynamic NUCA Before fetching a into its L1$, a CPU needs to find the L2 cache storing the line CPU L1$ L2$ CPU L1$ CPU L1$ CPU L1$ CPU L1$ CPU L1$ CPU L1$ CPU L1$ L2$ CMP (Chip Multi Processor)

27 27 Simulation Setup 16 processors, 64 L2 cache banks PARSEC and SPLASH-2 benchmarks Vanilla Wormhole NoC Simulation account for bus latency, arbitration time, etc.

28 28 Simulation Results Performance improvement in BENoC compared to a NoC-based CMP (a) average read transaction latency; (b) application speed

29 29 Summary Current NoCs are largely distributed Borrowing concepts from off-chip networks On-chip environment provides an opportunity Enhancing the network with a bus gives the best of both worlds Advanced services are easily supported Anycast, management and control Cost effective Power and performance Analysis and simulation

30 30 Thank you! Questions? zigi@tx.technion.ac.il Bus-Enhanced NoC QNoC Research Group Group Research QNoC


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