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SMV Example: Bus Protocol Ed Clarke Daniel Kroening Carnegie Mellon University.

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Presentation on theme: "SMV Example: Bus Protocol Ed Clarke Daniel Kroening Carnegie Mellon University."— Presentation transcript:

1 SMV Example: Bus Protocol Ed Clarke Daniel Kroening Carnegie Mellon University

2 Overview Node 1 Design goals: Collision free operation Priorities for the nodes Design goals: Collision free operation Priorities for the nodes Preliminaries: Single, shared bus Every node can broadcast on this bus Preliminaries: Single, shared bus Every node can broadcast on this bus Node 2 Node 3 Node 4 Similar busses are used in the automotive industry CAN Byteflight Similar busses are used in the automotive industry CAN Byteflight

3 Basic Idea Achieve design goals by: Assign unique time to each node Guarantees Collision free operation The node with the lower time gets priority Achieve design goals by: Assign unique time to each node Guarantees Collision free operation The node with the lower time gets priority Operation Principle Round based algorithm First person to start sending gets the bus Operation Principle Round based algorithm First person to start sending gets the bus

4 Example Node 1 Node 2 Node 3 Node 4 Bus time

5 Example Node 1 Node 2 Node 3 Node 4 Bus time Hm, I wont send

6 Example Node 1 Node 2 Node 3 Node 4 Bus time I will send!

7 Example Node 1 Node 2 Node 3 Node 4 Bus time

8 Example Node 1 Node 2 Node 3 Node 4 Bus time

9 Example Node 1 Node 2 Node 3 Node 4 Bus time

10 Example Node 1 Node 2 Node 3 Node 4 Bus time RESET CLOCK! Start of new Cycle

11 Example Node 1 Node 2 Node 3 Node 4 Bus time Hm, I wont send

12 SMV Model Design: A state machine controls each node Counter keeps track of clock Design: A state machine controls each node Counter keeps track of clock Counter: Reset if someone sends Increment otherwise Counter: Reset if someone sends Increment otherwise MODULE node(bus_active) VAR counter: ; ASSIGN next(counter):= case bus_active : 0; counter < 99: counter + 1; 1: 99; esac;

13 SMV Model Design: A state machine controls each node Counter keeps track of the clock Design: A state machine controls each node Counter keeps track of the clock Bus busy Skip Wait Sending bus_active beginning counter=priority

14 SMV Model MODULE node(priority, bus_active) VAR counter: ; state: { busy, skip, waiting, sending }; ASSIGN init(state):=busy; next(state):= case state=busy & beginning : { skip, waiting }; state=busy : busy; state=skip & bus_active : busy; state=skip : skip; state=waiting & bus_active : waiting; state=waiting & counter=priority: sending; state=waiting: waiting; state=sending: { busy, sending }; esac;

15 SMV Model MODULE main VAR node1: node(1, bus_active); node2: node(2, bus_active); node3: node(3, bus_active); node4: node(4, bus_active); DEFINE bus_active:=node1.is_sending | node2.is_sending | node3.is_sending | node4.is_sending;

16 Properties Desired Properties Safety: Only one node uses the bus at a given time Desired Properties Safety: Only one node uses the bus at a given time SPEC AG (node1.is_sending -> (!node2.is_sending & !node3.is_sending & !node4.is_sending)) SPEC AG (node2.is_sending -> (!node1.is_sending & !node3.is_sending & !node4.is_sending)) SPEC AG (node3.is_sending -> (!node1.is_sending & !node2.is_sending & !node4.is_sending)) SPEC AG (node4.is_sending -> (!node1.is_sending & !node2.is_sending & !node3.is_sending)) SPEC AG (node1.is_sending -> (!node2.is_sending & !node3.is_sending & !node4.is_sending)) SPEC AG (node2.is_sending -> (!node1.is_sending & !node3.is_sending & !node4.is_sending)) SPEC AG (node3.is_sending -> (!node1.is_sending & !node2.is_sending & !node4.is_sending)) SPEC AG (node4.is_sending -> (!node1.is_sending & !node2.is_sending & !node3.is_sending))

17 Properties Desired Properties Liveness: a node that is waiting for the bus will eventually get it, given that the nodes with higher priority are fair Desired Properties Liveness: a node that is waiting for the bus will eventually get it, given that the nodes with higher priority are fair FAIRNESS node1.is_skipping FAIRNESS node1.is_skipping & node2.is_skipping FAIRNESS node1.is_skipping & node2.is_skipping & node3.is_skipping SPEC AG AF bus_active SPEC AG(node1.is_waiting -> AF node1.is_sending) SPEC AG(node2.is_waiting -> AF node2.is_sending) SPEC AG(node3.is_waiting -> AF node3.is_sending) SPEC AG(node4.is_waiting -> AF node4.is_sending) FAIRNESS node1.is_skipping FAIRNESS node1.is_skipping & node2.is_skipping FAIRNESS node1.is_skipping & node2.is_skipping & node3.is_skipping SPEC AG AF bus_active SPEC AG(node1.is_waiting -> AF node1.is_sending) SPEC AG(node2.is_waiting -> AF node2.is_sending) SPEC AG(node3.is_waiting -> AF node3.is_sending) SPEC AG(node4.is_waiting -> AF node4.is_sending)


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