1. Lecture 21Comp. Arch. Fall 2006 Chapter 8: I/O Systems (continued) Adapted from Mary Jane Irwin at Penn State University for Computer Organization and Design, Patterson & Hennessy, © 2005 Computer Organization and Architecture, William Stallings, 7 th Edition Fundamentals of Computer Organization and Design, S. Dandamudi Springer, 2003

2. Lecture 21Comp. Arch. Fall 2006 A Typical I/O System Processor Cache Memory - I/O Bus Main Memory I/O Controller Disk I/O Controller I/O Controller Graphics Network Interrupts Disk

3. Lecture 21Comp. Arch. Fall 2006 Bus Hierarchy

4. Lecture 21Comp. Arch. Fall 2006 PCI Bus – Example of a Synchronous Bus Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines

5. Lecture 21Comp. Arch. Fall 2006 PCI Bus Lines (required) Systems lines l Including clock and reset Address & Data l 32 time multiplexed lines for address and data l Interrupt & validate lines Interface Control Arbitration l Not shared l Direct connection to PCI bus arbiter Error lines

6. Lecture 21Comp. Arch. Fall 2006 PCI Bus Lines (Optional) Interrupt lines l Not shared Cache support 64-bit Bus Extension l Additional 32 lines l Time multiplexed l 2 lines to enable devices to agree to use 64-bit transfer JTAG/Boundary Scan l For testing procedures

7. Lecture 21Comp. Arch. Fall 2006 PCI Commands Transaction between initiator (master) and target Master claims bus Determine type of transaction l e.g. I/O read/write Address phase One or more data phases

8. Lecture 21Comp. Arch. Fall 2006 PCI Read Timing Diagram for a block of size 3 1 st – occurs ASAP, 2 nd – target not ready for 1 cycle, 3 rd – initiator not ready for 1 cycle

9. Lecture 21Comp. Arch. Fall 2006 PCI Read Timing Diagram Draw a timing diagram for a PCI read operation (similar to example). Assume that 2 data transfers occur and that the following occurs during these transfers: during the first data transfer the initiator is not ready for two clock cycles, and during the second data transfer the target is not ready for one clock cycle. On your diagram clearly indicate: the address phase, data phase(s) and any wait states which wire(s) are controlled by the target device and which are controlled by the initiator device when the target reads the data off the bus

10. Lecture 21Comp. Arch. Fall 2006 The Need for Bus Arbitration Multiple devices may need to use the bus at the same time so must have a way to arbitrate multiple requests Bus arbitration schemes usually try to balance: l Bus priority – the highest priority device should be serviced first l Fairness – even the lowest priority device should never be completely locked out from the bus Bus arbitration schemes can be divided into four classes l Daisy chain arbitration – see next slide l Centralized, parallel arbitration – see next-next slide l Distributed arbitration by self-selection – each device wanting the bus places a code indicating its identity on the bus l Distributed arbitration by collision detection – device uses the bus when its not busy and if a collision happens (because some other device also decides to use the bus) then the device tries again later (Ethernet)

11. Lecture 21Comp. Arch. Fall 2006 Daisy Chain Bus Arbitration Advantage: simple Disadvantages: l Cannot assure fairness – a low-priority device may be locked out indefinitely l Slower – the daisy chain grant signal limits the bus speed Bus Arbiter Device 1 Highest Priority Device N Lowest Priority Device 2 Ack Release Request wired-OR Data/Addr

12. Lecture 21Comp. Arch. Fall 2006 Centralized Parallel Arbitration Advantages: flexible, can assure fairness Disadvantages: more complicated arbiter hardware Used in essentially all processor-memory buses and in high-speed I/O buses Bus Arbiter Device 1 Device NDevice 2 Ack1 Data/Addr Ack2 AckN Request1Request2RequestN

13. Lecture 21Comp. Arch. Fall 2006 PCI Bus Arbiter

14. Lecture 21Comp. Arch. Fall 2006 Motivation for PCI Bus Hidden Arbitration

15. Lecture 21Comp. Arch. Fall 2006 PCI Bus Hidden Arbitration

16. Lecture 21Comp. Arch. Fall 2006 PCI Bus Hidden Arbitration

17. Lecture 21Comp. Arch. Fall 2006 Bus Bandwidth Determinates The bandwidth of a bus is determined by l Whether its is synchronous or asynchronous and the timing characteristics of the protocol used l The data bus width l Whether the bus supports block transfers or only word at a time transfers FirewireUSB 2.0 TypeI/O Data lines42 ClockingAsynchronousSynchronous Max # devices63127 Max length4.5 meters5 meters Peak bandwidth 50 MB/s (400 Mbps) 100 MB/s (800 Mbps) 0.2 MB/s (low) 1.5 MB/s (full) 60 MB/s (high)

18. Lecture 21Comp. Arch. Fall 2006 USB Universal Serial Bus l Originally developed in 1995 by a consortium including -Compaq, HP, Intel, Lucent, Microsoft, and Philips l USB 1.1 supports -Low-speed devices (1.5 Mbps) -Full-speed devices (12 Mbps) l USB 2.0 supports -High-speed devices –Up to 480 Mbps (a factor of 40 over USB 1.1) -Uses the same connectors –Transmission speed is negotiated on device-by-device basis

19. Lecture 21Comp. Arch. Fall 2006 USB (contd) Motivation for USB l Avoid device-specific interfaces -Eliminates multitude of interfaces –PS/2, serial, parallel, monitor, microphone, keyboard,… l Avoid non-shareable interfaces -Standard interfaces support only one device l Avoid I/O address space and IRQ problems -USB does not require memory or address space l Avoid installation and configuration problems -Dont have to open the box to install and configure jumpers l Allow hot attachment of devices

20. Lecture 21Comp. Arch. Fall 2006 USB (contd) Additional advantages of USB l Power distribution -Simple devices can be bus-powered –Examples: mouse, keyboards, floppy disk drives, wireless LANs, coffee warmers, reading lights, MP3 players, … l Control peripherals -Possible because USB allows data to flow in both directions l Expandable through hubs l Power conservation -Enters suspend state if there is no activity for 3 ms l Error detection and recovery -Uses CRC

21. Lecture 21Comp. Arch. Fall 2006 USB (contd) USB encoding l Uses NRZI encoding -Non-Return to Zero-Inverted

22. Lecture 21Comp. Arch. Fall 2006 USB (contd) NRZI encoding l A signal transition occurs if the next bit is zero -It is called differential encoding l Two desirable properties -Signal transitions, not levels, need to be detected -Long string of zeros causes signal changes l Still a problem -Long strings of 1s do not causes signal change l To solve this problem -Uses bit stuffing –A zero is inserted after every six consecutive 1s

23. Lecture 21Comp. Arch. Fall 2006 USB (contd) Bit stuffing

24. Lecture 21Comp. Arch. Fall 2006 USB (contd) Transfer types -Four types of transfer l Interrupt transfer -Uses polling –Polling interval can range from 1 ms to 255 ms l Isochronous transfer -Used in real-time applications that require constant data transfer rate –Example: Reading audio from CD-ROM -These transfers are scheduled regularly -Do not use error detection and recovery

25. Lecture 21Comp. Arch. Fall 2006 USB (contd) l Control transfer -Used to configure and set up USB devices -Three phases –Setup stage »Conveys type of request made to target device –Data stage »Optional stage »Control transfers that require data use this stage –Status stage »Checks the status of the operation -Allocates a guaranteed bandwidth of 10% -Error detection and recovery are used –Recovery is by means of retries

26. Lecture 21Comp. Arch. Fall 2006 USB (contd) l Bulk transfer -For devices with no specific data transfer rate requirements –Example: sending data to a printer -Lowest priority bandwidth allocation -If the other three types of transfers take 100% of the bandwidth –Bulk transfers are deferred until load decreases -Error detection and recovery are used –Recovery is by means of retries

27. Lecture 21Comp. Arch. Fall 2006 USB (contd) USB architecture l USB host controller -Initiates transactions over USB l Root hub -Provides connection points l Two types of host controllers -Open host controller (OHC) –Defined by Intel -Universal host controller (UHC) –Specified by National Semiconductor, Microsoft, Compaq -Difference between the two –How they schedule the four types of transfers

28. Lecture 21Comp. Arch. Fall 2006 USB (contd) UHC scheduling l Schedules periodic transfers first -Periodic transfers: isochronous and interrupts -Can take up to 90% of bandwidth l These transfers are followed by control and bulk transfers -Control transfers are guaranteed 10% of bandwidth l Bulk transfers are scheduled only if there is bandwidth available

29. Lecture 21Comp. Arch. Fall 2006 USB (contd)

30. Lecture 21Comp. Arch. Fall 2006 USB (contd) OHC scheduling l Different from UHC scheduling l Reserves space for non-periodic transfers first -Non-periodic transfers: control and bulk -10% bandwidth reserved l Next periodic transfers are scheduled -Guarantees 90% bandwidth l Left over bandwidth is allocated to non-periodic transfers

31. Lecture 21Comp. Arch. Fall 2006 USB (contd) Bus powered devices l Low-power -Less than 100 mA -Can be bus-powered l High-powered -Between 100 mA and 500 mA –Full-powered ports can power these devices -Can be designed to have their own power -Operate in three modes –Configured (500 mA) –Unconfigured (100 mA) –Suspended ( about 2.5 mA)

32. Lecture 21Comp. Arch. Fall 2006 USB (contd) USB hubs l Bus-powered -No extra power supply required -Must be connected to an upstream port that can supply 500 mA -Downstream ports can only supply 100 mA –Number of ports is limited to four –Support only low-powered devices l Self-powered -Support 4 high-powered devices -Support 4 bus-powered USB hubs l Most 4-port hubs are dual-powered

33. Lecture 21Comp. Arch. Fall 2006 USB (contd) Hubs can be used to expand Upstream port Downstream ports

34. Lecture 21Comp. Arch. Fall 2006 USB (contd) USB transactions l Transfers are done in one or more transactions -Each transaction consists of several packets l Transactions may have between 1 and 3 phases -Token packet phase –Specifies transaction type and target device address -Data packet phase (optional) –Maximum of 1023 bytes are transferred -Handshake packet phase –Except for isochronous transfers, others use error detection for guaranteed delivery –Provides feedback on whether data has been received without error

35. Lecture 21Comp. Arch. Fall 2006 USB (contd) USB IRP frame

36. Lecture 21Comp. Arch. Fall 2006 USB (contd) Specifies token, data, or handshake packet Complement of type field Token packets use CRC-5 Hardware encoded special pattern

37. Lecture 21Comp. Arch. Fall 2006 USB (contd) USB 1.1 transactions

38. Lecture 21Comp. Arch. Fall 2006 USB (contd) USB 2.0 l USB 1.1 uses 1 ms frames USB 2.0 uses 125 s frames -1/8 of USB 1.1 l Supports 40X data rates -Up to 480 Mbps l Competitive with -SCSI -IEEE 1394 (FireWire) l Current standard

39. Lecture 21Comp. Arch. Fall 2006 IEEE 1394 Apple originally developed this standard for high-speed peripherals l Known by a variety of names -Apple: FireWire -Sony: i.ILINK l IEEE standardized it as IEEE 1394 -First released in 1995 as IEEE 1394-1995 -A slightly revised version as 1394a -Next version 1394b l Shares many of the features of USB

40. Lecture 21Comp. Arch. Fall 2006 IEEE 1394 (contd) Advantages l High speed -Supports three speeds –100, 200, 400 Mbps »Competes with USB 2.0 –Plans to boost it to 3.2 Gbps l Hot attachment -Like USB -No need to shut down power to attach devices l Peer-to-peer support -USB is processor-centric -Supports peer-to-peer communication without involving the processor

41. Lecture 21Comp. Arch. Fall 2006 IEEE 1394 (contd) l Expandable bus -Devices can be connected in daisy-chain fashion -Hubs can used to expand l Power distribution -Like the USB, cables distribute power –Much higher power than USB »Voltage between 8 and 33 V »Current an be up to 1.5 Amps l Error detection and recovery -As in USB, uses CRC -Uses retransmission in case of error l Long cables -Like the USB

42. Lecture 21Comp. Arch. Fall 2006 Example: The Pentium 4s Buses System Bus (Front Side Bus): 64b x 800 MHz (6.4GB/s), 533 MHz, or 400 MHz 2 serial ATAs: 150 MB/s 8 USBs: 60 MB/s 2 parallel ATA: 100 MB/s Hub Bus: 8b x 266 MHz Memory Controller Hub (Northbridge) I/O Controller Hub (Southbridge) Gbit ethernet: 0.266 GB/s DDR SDRAM Main Memory Graphics output: 2.0 GB/s PCI: 32b x 33 MHz

43. Lecture 21Comp. Arch. Fall 2006 Buses in Transition Companies are transitioning from synchronous, parallel, wide buses to asynchronous narrow buses l Reflection on wires and clock skew makes it difficult to use 16 to 64 parallel wires running at a high clock rate (e.g., ~400 MHz) so companies are transitioning to buses with a few one- way wires running at a very high clock rate (~2 GHz) PCIPCI express ATASerial ATA Total # wires12036807 # data wires32 – 64 (2-way) 2 x 4 (1-way) 16 (2-way) 2 x 2 (1-way) Clock (MHz)33 – 13363550150 Peak BW (MB/s)128 – 1064300100375 (3 Gbps)

44. Lecture 21Comp. Arch. Fall 2006 ATA Cable Sizes Serial ATA cables (red) are much thinner than parallel ATA cables (green)

45. Lecture 21Comp. Arch. Fall 2006 Communication of I/O Devices and Processor How the processor directs the I/O devices l Special I/O instructions -Must specify both the device and the command l Memory-mapped I/O -Portions of the high-order memory address space are assigned to each I/O device -Read and writes to those memory addresses are interpreted as commands to the I/O devices -Load/stores to the I/O address space can only be done by the OS How the I/O device communicates with the processor l Polling – the processor periodically checks the status of an I/O device to determine its need for service -Processor is totally in control – but does all the work -Can waste a lot of processor time due to speed differences l Interrupt-driven I/O – the I/O device issues an interrupts to the processor to indicate that it needs attention

46. Lecture 21Comp. Arch. Fall 2006 Interrupt-Driven Input add sub and or beq lbu sb... jr memory user program 1. input interrupt input interrupt service routine Processor Receiver Memory : Keyboard

47. Lecture 21Comp. Arch. Fall 2006 Interrupt-Driven Input memory user program 1. input interrupt 2.1 save state Processor Receiver Memory add sub and or beq lbu sb... jr 2.2 jump to interrupt service routine 2.4 return to user code Keyboard 2.3 service interrupt input interrupt service routine

48. Lecture 21Comp. Arch. Fall 2006 Interrupt-Driven Output Processor Trnsmttr Memory Display add sub and or beq lbu sb... jr memory user program 1.output interrupt 2.1 save state output interrupt service routine 2.2 jump to interrupt service routine 2.4 return to user code 2.3 service interrupt

49. Lecture 21Comp. Arch. Fall 2006 Interrupt-Driven I/O An I/O interrupt is asynchronous wrt instruction execution l Is not associated with any instruction so doesnt prevent any instruction from completing -You can pick your own convenient point to handle the interrupt With I/O interrupts l Need a way to identify the device generating the interrupt l Can have different urgencies (so may need to be prioritized) Advantages of using interrupts l Relieves the processor from having to continuously poll for an I/O event; user program progress is only suspended during the actual transfer of I/O data to/from user memory space Disadvantage – special hardware is needed to l Cause an interrupt (I/O device) and detect an interrupt and save the necessary information to resume normal processing after servicing the interrupt (processor)

50. Lecture 21Comp. Arch. Fall 2006 Direct Memory Access (DMA) For high-bandwidth devices (like disks) interrupt-driven I/O would consume a lot of processor cycles DMA – the I/O controller has the ability to transfer data directly to/from the memory without involving the processor 1. The processor initiates the DMA transfer by supplying the I/O device address, the operation to be performed, the memory address destination/source, the number of bytes to transfer 2. The I/O DMA controller manages the entire transfer (possibly thousand of bytes in length), arbitrating for the bus 3. When the DMA transfer is complete, the I/O controller interrupts the processor to let it know that the transfer is complete There may be multiple DMA devices in one system l Processor and I/O controllers contend for bus cycles and for memory

51. Lecture 21Comp. Arch. Fall 2006 The DMA Stale Data Problem In systems with caches, there can be two copies of a data item, one in the cache and one in the main memory l For a DMA read (from disk to memory) – the processor will be using stale data if that location is also in the cache l For a DMA write (from memory to disk) and a write-back cache – the I/O device will receive stale data if the data is in the cache and has not yet been written back to the memory The coherency problem is solved by 1. Routing all I/O activity through the cache – expensive and a large negative performance impact 2. Having the OS selectively invalidate the cache for an I/O read or force write-backs for an I/O write (flushing) 3. Providing hardware to selectively invalidate or flush the cache – need a hardware snooper (details in Lecture 25)

52. Lecture 21Comp. Arch. Fall 2006 I/O and the Operating System The operating system acts as the interface between the I/O hardware and the program requesting I/O l To protect the shared I/O resources, the user program is not allowed to communicate directly with the I/O device Thus OS must be able to give commands to I/O devices, handle interrupts generated by I/O devices, provide equitable access to the shared I/O resources, and schedule I/O requests to enhance system throughput l I/O interrupts result in a transfer of processor control to the supervisor (OS) process