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JR.S00 1 Lecture 15: Busses and Networking (1) Prof. Jan Rabaey Computer Science 252, Spring 2000 Based on slides from Dave Patterson, John Kubiatowicz.

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Presentation on theme: "JR.S00 1 Lecture 15: Busses and Networking (1) Prof. Jan Rabaey Computer Science 252, Spring 2000 Based on slides from Dave Patterson, John Kubiatowicz."— Presentation transcript:

1 JR.S00 1 Lecture 15: Busses and Networking (1) Prof. Jan Rabaey Computer Science 252, Spring 2000 Based on slides from Dave Patterson, John Kubiatowicz Bill Dally, and Sonics, Inc

2 JR.S00 2 A Communication-Centric World Computation is getting distributed … –Internet, WAN, LAN, BodyLAN, Home Networks, Microprocessor Peripherals, Processor-Memory Interface, System-on-a-Chip Efficient Networking and Communication is Crucial The System-on-a-Chip implies the Network- on-a-Chip In Next Set of Lectures: –Busses and Networks –But more importantly, the impact of integration

3 JR.S00 3 A Bus Is: shared communication link single set of wires used to connect multiple subsystems A Bus is also a fundamental tool for composing large, complex systems –systematic means of abstraction Control Datapath Memory Processor Input Output What is a bus?

4 JR.S00 4 Busses

5 JR.S00 5 Versatility: –New devices can be added easily –Peripherals can be moved between computer systems that use the same bus standard Low Cost: –A single set of wires is shared in multiple ways Memory Processer I/O Device Advantages of Buses

6 JR.S00 6 It creates a communication bottleneck –The bandwidth of that bus can limit the maximum I/O throughput The maximum bus speed is largely limited by: –The length of the bus –The number of devices on the bus –The need to support a range of devices with: »Widely varying latencies »Widely varying data transfer rates Memory Processor I/O Device Disadvantage of Buses

7 JR.S00 7 Control lines: –Signal requests and acknowledgments –Indicate what type of information is on the data lines Data lines carry information between the source and the destination: –Data and Addresses –Complex commands Data Lines Control Lines General Organization of a Bus

8 JR.S00 8 A bus transaction includes two parts: –Issuing the command (and address) – request –Transferring the data – action Master is the one who starts the bus transaction by: –issuing the command (and address) Slave is the one who responds to the address by: –Sending data to the master if the master ask for data –Receiving data from the master if the master wants to send data Bus Master Bus Slave Master issues command Data can go either way Master versus Slave

9 JR.S00 9 Types of Busses Processor-Memory Bus (design specific) –Short and high speed –Only need to match the memory system »Maximize memory-to-processor bandwidth –Connects directly to the processor –Optimized for cache block transfers I/O Bus (industry standard) –Usually is lengthy and slower –Need to match a wide range of I/O devices –Connects to the processor-memory bus or backplane bus Backplane Bus (standard or proprietary) –Backplane: an interconnection structure within the chassis –Allow processors, memory, and I/O devices to coexist –Cost advantage: one bus for all components

10 JR.S00 10 Processor/Memory Bus PCI Bus I/O Busses Example: Pentium System Organization

11 JR.S00 11 A Computer System with One Bus: Backplane Bus A single bus (the backplane bus) is used for: –Processor to memory communication –Communication between I/O devices and memory Advantages: Simple and low cost Disadvantages: slow and the bus can become a major bottleneck Example: IBM PC - AT ProcessorMemory I/O Devices Backplane Bus

12 JR.S00 12 A Two-Bus System I/O buses tap into the processor-memory bus via bus adaptors: –Processor-memory bus: mainly for processor-memory traffic –I/O buses: provide expansion slots for I/O devices Apple Macintosh-II –NuBus: Processor, memory, and a few selected I/O devices –SCCI Bus: the rest of the I/O devices ProcessorMemory I/O Bus Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus

13 JR.S00 13 A Three-Bus System A small number of backplane buses tap into the processor-memory bus –Processor-memory bus is only used for processor-memory traffic –I/O buses are connected to the backplane bus Advantage: loading on the processor bus is greatly reduced ProcessorMemory Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus

14 JR.S00 14 North/South Bridge architectures: separate busses Separate sets of pins for different functions –Memory bus –Caches –Graphics bus (for fast frame buffer) –I/O busses are connected to the backplane bus Advantage: –Busses can run at different speeds –Much less overall loading! ProcessorMemory Processor Memory Bus Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus backside cache

15 JR.S00 15 Bunch of Wires Physical / Mechanical Characteristics – the connectors Electrical Specification Timing and Signaling Specification Transaction Protocol What defines a bus?

16 JR.S00 16 Synchronous Bus: –Includes a clock in the control lines –A fixed protocol for communication that is relative to the clock –Advantage: involves very little logic and can run very fast –Disadvantages: »Every device on the bus must run at the same clock rate »To avoid clock skew, they cannot be long if they are fast Asynchronous Bus: –It is not clocked –It can accommodate a wide range of devices –It can be lengthened without worrying about clock skew –It requires a handshaking protocol Synchronous and Asynchronous Bus

17 JR.S00 17 ° ° ° MasterSlave Control Lines Address Lines Data Lines Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing. Synchronous Bus Transfers: sequence relative to common clock. Busses so far

18 JR.S00 18 Bus Transaction Arbitration: Who gets the bus Request: What do we want to do Action: What happens in response

19 JR.S00 19 One of the most important issues in bus design: –How is the bus reserved by a device that wishes to use it? Chaos is avoided by a master-slave arrangement: –Only the bus master can control access to the bus: It initiates and controls all bus requests –A slave responds to read and write requests The simplest system: –Processor is the only bus master –All bus requests must be controlled by the processor –Major drawback: the processor is involved in every transaction Bus Master Bus Slave Control: Master initiates requests Data can go either way Arbitration: Obtaining Access to the Bus

20 JR.S00 20 Multiple Potential Bus Masters: the Need for Arbitration Bus arbitration scheme: –A bus master wanting to use the bus asserts the bus request –A bus master cannot use the bus until its request is granted –A bus master must signal to the arbiter the end of the bus utilization Bus arbitration schemes usually try to balance two factors: –Bus priority: the highest priority device should be serviced first –Fairness: Even the lowest priority device should never be completely locked out from the bus Bus arbitration schemes can be divided into four broad classes: –Daisy chain arbitration –Centralized, parallel arbitration –Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. –Distributed arbitration by collision detection: Each device just goes for it. Problems found after the fact.

21 JR.S00 21 The Daisy Chain Bus Arbitrations Scheme Advantage: simple Disadvantages: –Cannot assure fairness: A low-priority device may be locked out indefinitely –The use of the daisy chain grant signal also limits the bus speed Bus Arbiter Device 1 Highest Priority Device N Lowest Priority Device 2 Grant Release Request wired-OR

22 JR.S00 22 Used in essentially all processor-memory busses and in high-speed I/O busses Bus Arbiter Device 1 Device N Device 2 Grant Req Centralized Parallel Arbitration

23 JR.S00 23 All agents operate synchronously All can source / sink data at same rate => simple protocol –just manage the source and target Simplest bus paradigm

24 JR.S00 24 Even memory busses are more complex than this –memory (slave) may take time to respond –it may need to control data rate BReq BG Cmd+Addr R/W Address Data1Data2 Data Simple Synchronous Protocol

25 JR.S00 25 Slave indicates when it is prepared for data xfer Actual transfer goes at bus rate BReq BG Cmd+Addr R/W Address Data1Data2 Data Data1 Wait Typical Synchronous Protocol

26 JR.S00 26 Separate versus multiplexed address and data lines: –Address and data can be transmitted in one bus cycle if separate address and data lines are available –Cost: (a) more bus lines, (b) increased complexity Data bus width: –By increasing the width of the data bus, transfers of multiple words require fewer bus cycles –Example: SPARCstation 20s memory bus is 128 bit wide –Cost: more bus lines Block transfers: –Allow the bus to transfer multiple words in back-to-back bus cycles –Only one address needs to be sent at the beginning –The bus is not released until the last word is transferred –Cost: (a) increased complexity (b) decreased response time for request Increasing the Bus Bandwidth

27 JR.S00 27 Overlapped arbitration –perform arbitration for next transaction during current transaction Bus parking –master holds onto bus and performs multiple transactions as long as no other master makes request Overlapped address / data phases –requires one of the above techniques Split-phase (or packet switched) bus –completely separate address and data phases –arbitrate separately for each –address phase yield a tag which is matched with data phase All of the above in most modern memory buses Increasing Transaction Rate on Multimaster Bus

28 JR.S00 28 BusMBusSummitChallengeXDBus OriginatorSunHPSGISun Clock Rate (MHz)40604866 Address lines364840muxed Data lines64128256144 (parity) Data Sizes (bits)2565121024512 Clocks/transfer454? Peak (MB/s)320(80)96012001056 MasterMultiMultiMultiMulti ArbitrationCentralCentralCentralCentral Slots16910 Busses/system1112 Length13 inches12? inches17 inches 1993 CPU- Memory Bus Survey

29 JR.S00 29 Address Data Read Req Ack Master Asserts Address Master Asserts Data Next Address Write Transaction t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack Asynchronous Handshake (4-phase)

30 JR.S00 30 Address Data Read Req Ack Master Asserts AddressNext Address t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack Read Transaction Slave Data

31 JR.S00 31 BusSBusTurboChannelMicroChannelPCI OriginatorSunDECIBMIntel Clock Rate (MHz)16-2512.5-25async33 AddressingVirtualPhysicalPhysicalPhysical Data Sizes (bits)8,16,328,16,24,328,16,24,32,648,16,24,32,64 MasterMultiSingleMultiMulti ArbitrationCentralCentralCentralCentral 32 bit read (MB/s)33252033 Peak (MB/s)898475111 (222) Max Power (W)16261325 1993 Backplane/IO Bus Survey

32 JR.S00 32 Examples –graphics –fast networks Limited number of devices Data transfer bursts at full rate DMA transfers important –small controller spools stream of bytes to or from memory Either side may need to squelch transfer –buffers fill up High Speed I/O Bus

33 JR.S00 33 All signals sampled on rising edge Centralized Parallel Arbitration –overlapped with previous transaction All transfers are (unlimited) bursts Address phase starts by asserting FRAME# Next cycle initiator asserts cmd and address Data transfers happen on when –IRDY# asserted by master when ready to transfer data –TRDY# asserted by target when ready to transfer data –transfer when both asserted on rising edge FRAME# deasserted when master intends to complete only one more data transfer PCI Read/Write Transactions

34 JR.S00 34 – Turn-around cycle on any signal driven by more than one agent PCI Read Transaction

35 JR.S00 35 PCI Write Transaction

36 JR.S00 36 The System-on-a-Chip Nightmare Bridge DMACPUDSP Mem Ctrl. MPEG C IOO System Bus Peripheral Bus Control Wires Custom Interfaces The Board-on-a-Chip Approach

37 JR.S00 37 Sonics SOC Integration Architecture SiliconBackplane Agent Open Core Protocol SiliconBackplane (patented) MultiChip Backplane { DSP MPEG CPU DMA C MEM IO

38 JR.S00 38 Open Core Protocol Goals Bus Independent Scalable Configurable Synthesis/Timing Analysis Friendly Encompass entire core/system interface needs (data, control, and test flows)

39 JR.S00 39 Data, Control, and Test Flows Data Flow –Signals and protocols associated with moving data –Includes address, data, handshaking, etc. –Similar to services provided by traditional computer buses Control Flow –Signals and protocols associated with non-data communication –Sideband - not synchronized to data flow (out of band) –Examples include interrupts, high-level flow control, etc. Test Flow –Signals and protocols related to debug and manufacturing test

40 JR.S00 40 OCP Overview Point-to-point, uni-directional, synchronous –easy physical implementation Master/Slave, request/response –well-defined, simple roles Extensions –added functionality to support cores with more complex interface requirements Configurability –pay only for the features needed for a given core

41 JR.S00 41 Master vs. Slave IP Core On-Chip Bus Slave MasterSlave Master InitiatorTarget Open Core Protocol Request Response

42 JR.S00 42 Basic OCP Master MCmd [3] MAddr [N] MData [N] SResp [3] SData [N] Clk SCmdAccept Read: Command, Address Command Accept Response, Data Write (posted): Command, Address, Data Command Accept MCmd, MAddr SCmdAccept SResp, SData MCmd, Maddr, MData SCmdAccept Slave

43 JR.S00 43 Protocol Phases Request Phase (begins Transfer) –Master presents request (command, address, etc.) to Slave Response Phase (ends Transfer) –Slave presents response (success/fail, read data) to Master –Only available for read transfers (posted write model) Datahandshake Phase (Optional) –Allows pipelining request ahead of write data –Only available for write transfers Phase ordering –Request -> Datahandshake -> Response

44 JR.S00 44 OCP Extensions Simple Extensions –Byte Enables –Bursts –Flow Control –Data Handshake Complex Extensions –Threads and Connections Sideband Signals

45 JR.S00 45 The Backplane: Why Not Use a Computer Bus? IP Core IP Core IP Core IP Core Computer Bus Transmit FIFOReceive FIFO Time Data ArbiterAddress Expensive to decouple Not designed for real-time

46 JR.S00 46 Communication Buses Decouple and Guarantee Real Time IP Core IP Core IP Core IP Core Communications Bus Transmit FIFOReceive FIFO Time Data TDMA Connections are expensive Poor read latency

47 JR.S00 47 From Communications Efficient BW decoupling Guaranteed BW & latency Side-band signaling SiliconBackplane Employs Best of Both From Computing Address-based selection Write and read transfers Pipelining DSP MPEG CPU DMA C MEM IO

48 JR.S00 48 Guaranteed Bandwidth Arbitration Independent arbitration for every cycle includes two phases: -Distributed TDMA -Round robin Provides fine control over system bandwidth Current Slot Arbitration Command

49 JR.S00 49 Guaranteed Latency Fixed latency between command/address and data/response phases Matches pipelined CPU model ensuring high performance access to on-chip resources Pipelined data routed through SiliconBackplane Latency re-programmable in software Variable-latency blocks do not tie up the SiliconBackplane

50 JR.S00 50 Pipeline Diagram

51 JR.S00 51 Integrated Signaling Mechanism Dedicated SiliconBackplane wires ( Flags ) support: –Bus-style out-of-band signaling (interrupts) –Point-to-point communications (flow control) –Dynamic point-to-point (retry mechanism) Same design flow, timing, flexibility as address/data portion of SonicsIA

52 JR.S00 52 MultiChip Backplane SiliconBackplane MultiChip Backplane Extends SonicsIA Between Chips CPU-Based ASSP ASSP FPGA Seamless integration of protocols

53 JR.S00 53 Validation / Test SiliconBackplane highly visible for test –All subsystems communicate through SiliconBackplane Test Interfaces: –MultiChip Backplane: 100s MB/sec. –ServiceAgent: Scan-based Each subsystem can be tested/validated stand-alone Test Vectors Test Vectors MultiChip Backplane

54 JR.S00 54 Summary Busses are an important technique for building large-scale systems –Their speed is critically dependent on factors such as length, number of devices, etc. –Critically limited by capacitance –Tricks: esoteric drive technology such as GTL Important terminology: –Master: The device that can initiate new transactions –Slaves: Devices that respond to the master Two types of bus timing: –Synchronous: bus includes clock –Asynchronous: no clock, just REQ/ACK strobing System-on-a-Chip approach invites new solutions –Well-defined and clear communication protocols –Physical layer hidden to designer

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