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Switching - Fabric An Engineering Approach to Computer Networking

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April 3, 2000Communication Networks2 Switching Number of connections: from few (4 or 8) to huge (100K)

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April 3, 2000Communication Networks3 Switching - Basic Assumptions continuous streams telephone connections no bursts no buffers connections change multicast Blocking external internal re-arrangeable strict sense non-blocking wide sense non-blocking

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April 3, 2000Communication Networks4 Multiplexors and demultiplexors Multiplexor: aggregates sessions N input lines Output runs N times as fast as input Demultiplexor: distributes sessions one input line and N outputs that run N times slower Can cascade multiplexors

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April 3, 2000Communication Networks5 Time division switching Key idea: when demultiplexing, position in frame determines output limk Time division switching interchanges sample position within a frame: time slot interchange (TSI)

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April 3, 2000Communication Networks6 Example - TSI sessions: (1,2) (2,4) (3,1) (4,3) TSI

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April 3, 2000Communication Networks7 TSI Simple to build. Multicast Limit is the time taken to read and write to memory For 120,000 circuits need to read and write memory once every 125 microseconds each operation takes around 0.5 ns => impossible with current technology Need to look to other techniques

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April 3, 2000Communication Networks8 Space division switching Each sample takes a different path through the switch, depending on its destination

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April 3, 2000Communication Networks9 Crossbar Simplest possible space-division switch Crosspoints can be turned on or off

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April 3, 2000Communication Networks10 Crossbar - example sessions: (1,2) (2,4) (3,1) (4,3)

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April 3, 2000Communication Networks11 Crossbar Advantages: simple to implement simple control strict sense non-blocking Drawbacks number of crosspoints, N 2 large VLSI space vulnerable to single faults

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April 3, 2000Communication Networks12 Time-space switching Precede each input trunk in a crossbar with a TSI Delay samples so that they arrive at the right time for the space division switchs schedule MUXMUX MUXMUX

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April 3, 2000Communication Networks13 Time-Space: Example TSI Internal speed = double link speed time 1 time 2

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April 3, 2000Communication Networks14 Finding the schedule Build a graph nodes - input links session connects an input and output nodes. Feasible schedule Computing a schedule compute perfect matching.

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April 3, 2000Communication Networks15 Time-space-time (TST) switching Allowed to flip samples both on input and output trunk Gives more flexibility => lowers call blocking probability

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April 3, 2000Communication Networks16 Circuit switching - Space division graph representation transmitter nodes receiver nodes internal nodes Feasible schedule edge disjoint paths. cost function number of crosspoints internal nodes

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April 3, 2000Communication Networks17 Example sessions: (1,3) (2,6) (3,1) (4,4) (5,2) (6,5)

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April 3, 2000Communication Networks18 Clos Network Clos(N, n, k) N - inputs/outputs; nxk(N/n)x(N/n) kxn N=6 n=2 k=2 3x3 2x2

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April 3, 2000Communication Networks19 Clos Network - strict sense non-blocking Holds for k >= 2n-1 Proof: Consider and idle input and output Input box connected to at most n-1 middle layer switches output box connected to at most n-1 middle layer switches There exists a "free" middle switch.

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April 3, 2000Communication Networks20 Proof

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April 3, 2000Communication Networks21 Example Clos(8,2,3) N=8 n=2 k=3 4x4 3x2 2x3 4x43x2

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April 3, 2000Communication Networks22 Clos Network - rearrangable Holds for k >= n Proof: Consider all input and output find a perfect matching. route the perfect matching remaining network is Clos(N-n,n-1,k-1) summary: smaller circuit weaker guarantee Mulicast ?

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April 3, 2000Communication Networks23 Rearrangable Clos Network – routing algorithm n Start at some arbitrary 2x2 input switch, and route it to its destination through the upper switch. n Route the other output port of the 2x2 switch you reached to its input port through the lower switch. n If the other port in the input switched you reached has not been routed yet, route it through the upper middle switch. Otherwise, select an arbitrary input port switch that was not yet used, and repeat the procedure.

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April 3, 2000Communication Networks24 Recursive constructions N/2 x N/ n 1 n

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April 3, 2000Communication Networks25 Algorithm Complexity N routing steps for each level Log n levels to do ===> N log n Given parallel hardware: O(N) time

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April 3, 2000Communication Networks26 Alternative View of the problem A graph coloring problem: Input/output switches = nodes A match = link Middle stage switches = colors This is the well known Coloring of bi-partite graph problem. Heuristics fail miserably!!!

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April 3, 2000Communication Networks27 Another algorithm – matrix based Specification matrix: Rows = input switches (n) Columns = middle switches (N/n = r) Content = output switches (1..n) We need an algorithms that will fill up the matrix with a feasible routing: Same number cannot appear in the same column Works also for CLOS with redundancy

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April 3, 2000Communication Networks28 Algorithm Principle For j=0,1,2,… balance the destination j among the columns Challenges: efficiency termination We describe an Algorithm by Lee, Hwang, and Carpinelli, T.COM. 44 (11), Nov 1996

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April 3, 2000Communication Networks29 The Matrix Meaning 0 1 4x4 3x2 2x3 4x43x2

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April 3, 2000Communication Networks30 Data Structures (j,e), j=0,1,…n-1, e=0,1,…,r-1 :- the set of rows {i} such that s ij =e 0(e), e=0,1,r-1 :- the set of columns {j} such that S i does not contain e 2(e), e=0,1,r-1 :- the set of columns {j} such that S i contains e at least twice

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April 3, 2000Communication Networks31 Algorithm Init: e=0 1. If 2(e) empty e e+1 if e=r stop; else goto 1 2. if 2(e) j 1 st element of 2(e) k 1 st element of 0(e) 3. (simple swap) i 1 st element of (j,e) if e< s ik swap s ij with s ik e s ik remove i from (j,e) and (k,e) add i to (j,e) and (k,e) if |(j,e)|=1 remove j from 2(e) if |(j,e)|=1 remove j from 0(e) if |(j,e)|=2 add j to 2(e) if |(k,e)|=0 add k to 0(e) if |(k,e)|=1 remove k from 2(e) remove k from 0(e) goto step 1 4. (Next Simple Swap) If e> s ik i 2 nd element of s ik repeat step 3 on i if e> s ik goto step 5 5. (Successive Swap) A. u e; remove k from 0(u) if if |(j,u)|=2 remove j from 2(u) B. v s ik swap s ij with s ik remove i from (j,u) and (k,v) add i to (j,v) and (k,u) C. if e

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April 3, 2000Communication Networks32 Algorithm Complexity adding an element to a set, choosing/removing the 1 st /2 nd element from a set take O(1) steps 5A 5B and 5D each take O(1) time removing a generally positioned element from an r-set takes O(r) time step 5C time complexity is in O(r) [ 2(v)-{k}, 0(v)-{j} ] the looping in step 5 does not contain step 5C, only 5B and 5D the time complexity for step 5 is O(r) Algorithm time complexity O(nr 2 )

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April 3, 2000Communication Networks33 Recursive constructions - Benes Network N/2 x N/ n 1 n

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April 3, 2000Communication Networks34 Clos network size Number of switching elements is given by for k=n (rearrangeable non-blocking) Optimal value for n is n=sqrt{2}N, which yields

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April 3, 2000Communication Networks35 a lower bound for the number of switching elements? Assume we have 2x2 switching units. We have N! switching permutation Can we achieve this bound?

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April 3, 2000Communication Networks36 Example 16x16

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April 3, 2000Communication Networks37 Benes Networks Size: 2 log N –1 stages N/2 switches in each stage N log 2 N –N/2 Rearrangeable Clos network with k=2 n=2 Symmetry Example. proof

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April 3, 2000Communication Networks38 Strict Sense non-Blocking N/2 x N/

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April 3, 2000Communication Networks39 Cantor Networks m copies of Benes network. For m >= log N its strict sense non-blocking Network size N log 2 N Example Proof.

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April 3, 2000Communication Networks40 Banyan Self routing! Size: log 2 N stages N/2 switches in each stage 0.5N log 2 N elements This is less than the lower bound!

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April 3, 2000Communication Networks41 Banyan

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April 3, 2000Communication Networks42 Other Banyans Omega or shuffle exchange

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April 3, 2000Communication Networks43 How do deal with internal blocking in Banyan speed – up internal buffers Batcher bitonic sorter

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April 3, 2000Communication Networks44

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