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Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Modular Performance Analysis with Real-Time Calculus Lothar Thiele,

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Presentation on theme: "Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Modular Performance Analysis with Real-Time Calculus Lothar Thiele,"— Presentation transcript:

1 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Modular Performance Analysis with Real-Time Calculus Lothar Thiele, Simon Künzli, Alex Maxiaguine, Ernesto Wandeler, et al. Computer Engineering and Networks Laboratory ETH Zurich, Switzerland 23. November 2005 Workshop on Distributed Embedded Systems, Leiden, The Netherlands

2 2 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Real-Time Calculus Developed at ETH Zurich since 2000 Based on: –Max-Plus/Min-Plus Algebra [Quadrat et al., 1992] –Network Calculus [Le Boudec & Thiran, 2001]

3 3 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Abstract Models for Performance Analysis Processor Task Input Stream Service Model Load Model Concrete Instance Abstract Representation Task / Processing Model

4 4 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Load Model t [ms] events Event Stream maximum / minimum arriving demand in any interval of length 2.5 ms 2.5 Arrival Curve & Delay d demand [ms] 2.5 number of events in in t=[ ] ms deadline = d Service Model Load Model Processing Model l u

5 5 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Load Model - Examples periodicperiodic w/ jitter periodic w/ burstcomplex Service Model Load Model Processing Model

6 6 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Service Model t [ms] availability Resource Availability maximum/minimum available service in any interval of length 2.5 ms available service in t=[ ] ms 2.5 u l Service Curves [ l, u ] service [ms] 2.5 Service Model Load Model Processing Model

7 7 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Service Model - Examples full resource bounded delay TDMA resourceperiodic resource Service Model Load Model Processing Model

8 8 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory d Task / Processing Model RTC Service Model Load Model Processing Model Real-Time Calculus

9 9 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Scheduling / Arbitration FP GPS EDF TDMA

10 10 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Analysis: Delay and Backlog delay d max backlog b max l u [ l, u ] RTC Service Model Load Model Processing Model

11 11 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Case Study ECU1 BUS CC1 ECU2CC2 ECU3CC3 S1 S2 S3 S4 S5 5 Real-Time Input Streams - with jitter - with bursts - deadline > period 3 ECUs with own CCs 12 Tasks & 7 Messages - with different WCED 2 Scheduling Policies - Earliest Deadline First (ECUs) - Fixed Priority (ECUs & CCs) Hierarchical Scheduling - Static & Dynamic Polling Servers Bus with TDMA - 4 time slots with different lengths (#1,#3 for CC1, #2 for CC3, #4 for CC3) Total Utilization: - ECU159 % - ECU287 % - ECU367 % - BUS56 %

12 12 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Specification Data

13 13 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory The Distributed Embedded System... ECU1BUS (TDMA) C1.1 C1.2 C2.1 C3.1 C4.1 C5.1 C3.2 T1.1 T1.3 T2.1 T3.1 T3.3 PS FP CC1 ECU2 T4.1 T5.1 FP CC2 ECU3 T1.2 FP CC3 T3.2 FP EDF T2.2 PS T4.2 PS T5.2 S1 S2 S3 S4 S5 S1 S3

14 14 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory... and its Real-Time Calculus Model S5 S4 S1 S2 S3 T1.1 T1.3 C4.1 C5.1 TDMA CPU T2.1 T3.1 T3.3 CPU T4.1 T5.1 CPU PS T1.2 EDF PS T3.2 C1.2 C3.2 C2.1 C3.1 C1.1 T5.2 T4.2 T2.2 PS ECU1 ECU2 ECU3 BUS CC1 CC2 CC3

15 15 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Input & Output of Stream 3 S5 S4 S1 S2 S3 T1.1 T1.3 C4.1 C5.1 TDMA CPU T2.1 T3.1 T3.3 CPU T4.1 T5.1 CPU PS T1.2 EDF PS T3.2 C1.2 C3.2 C2.1 C3.1 C1.1 T5.2 T4.2 T2.2 PS ECU1 ECU2 ECU3 BUS CC1 CC2 CC3

16 16 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Service Demand & Supply for EDF Block S5 S4 S1 S2 S3 T1.1 T1.3 C4.1 C5.1 TDMA CPU T2.1 T3.1 T3.3 CPU T4.1 T5.1 CPU PS T1.2 EDF PS T3.2 C1.2 C3.2 C2.1 C3.1 C1.1 T5.2 T4.2 T2.2 PS ECU1 ECU2 ECU3 BUS CC1 CC2 CC3

17 17 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Service Demand & Supply for EDF Block S5 S4 S1 S2 S3 T1.1 T1.3 C4.1 C5.1 TDMA CPU T2.1 T3.1 T3.3 CPU T4.1 T5.1 CPU PS T1.2 EDF PS T3.2 C1.2 C3.2 C2.1 C3.1 C1.1 T5.2 T4.2 T2.2 PS ECU1 ECU2 ECU3 BUS CC1 CC2 CC3

18 18 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Service Demand & Supply for EDF Block S5 S4 S1 S2 S3 T1.1 T1.3 C4.1 C5.1 TDMA CPU T2.1 T3.1 T3.3 CPU T4.1 T5.1 CPU PS T1.2 EDF PS T3.2 C1.2 C3.2 C2.1 C3.1 C1.1 T5.2 T4.2 T2.2 PS ECU1 ECU2 ECU3 BUS CC1 CC2 CC3

19 19 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Buffer Requirements S5 S4 S1 S2 S3 T1.1 T1.3 C4.1 C5.1 TDMA CPU T2.1 T3.1 T3.3 CPU T4.1 T5.1 CPU PS T1.2 EDF PS T3.2 C1.2 C3.2 C2.1 C3.1 C1.1 T5.2 T4.2 T2.2 PS ECU1 ECU2 ECU3 BUS CC1 CC2 CC

20 20 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Delay Guarantees S5 S4 S1 S2 S3 T1.1 T1.3 C4.1 C5.1 TDMA CPU T2.1 T3.1 T3.3 CPU T4.1 T5.1 CPU PS T1.2 EDF PS T3.2 C1.2 C3.2 C2.1 C3.1 C1.1 T5.2 T4.2 T2.2 PS ECU1 ECU2 ECU3 BUS CC1 CC2 CC

21 21 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory System Analysis Time Pentium Mobile 1.6GHz Matlab 7 RTC Kernel Prototype (Java 1.4)

22 22 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Tool Support Matlab Toolbox for Real-Time Calculus –Version 1.0 to be released December 2005 Simulink Frontend –Prototype under development

23 23 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Limitations of Real-Time Calculus High Level of Abstraction Time-Interval Domain

24 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Thank you! Ernesto Wandeler


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