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Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Barriers: Friend or Foe? Steve Blackburn Department of Computer.

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Presentation on theme: "Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Barriers: Friend or Foe? Steve Blackburn Department of Computer."— Presentation transcript:

1 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Barriers: Friend or Foe? Steve Blackburn Department of Computer Science Australian National University Tony Hosking Department of Computer Sciences Purdue University

2 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Read & Write Barrier Costs Are r/w barrier costs significant?

3 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Read and Write Barriers Algorithmically powerful mechanisms –Extend semantics of each read/write Particularly useful to GC Untested assumption: read/write barriers are expensive –Curtails creativity in GC algorithm development –Encourages (unnecessary?) work on avoidance Prior work –[Zorn 1990] (used simulation & traces) –[Blackburn & McKinley 2002] (compilation & inlining)

4 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Our Contributions Methodology for measurement Evaluate mutator overhead –5 common w/b, 2 r/b –9 benchmarks –3 architectures (AMD, P4, PPC) –Exclude compiler, GC from measurements

5 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Methodology Want to remove barrier –Compare with and without barrier Add full trace to generational collector –Remembered objects irrelevant –Can include/exclude barrier MMTk, Jikes RVM –Hardware performance counters –Pseudo-adaptive (realistic, deterministic) –Second iteration (avoid compiler overhead) –Best of 5 (least disturbed)

6 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Write Barrier Code 1 public final void writeBarrier(ObjectReference src, Address slot, 2 ObjectReference tgt, int mode) 3 throws InlinePragma { 4 // insert write barrier code here 5 slot.store (tgt); 6 }

7 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Write Barrier Code cont. JavaPPC asmx86 asm Boundary (Slot) 4 if (slot.LT(NURSERY_START) 5 && tgt.GE(NURSERY_START)) 6 remSlots.insert(slot); 1 liu R3,0x6e10 2 cmplW cr1,R30,R3 3 bge 1 54 4 liu R3,0x6e10 5 cmplW cr1,R31,R3 6 bge 1 7c 1 cmp edi 0xa0200000 2 jlge 0 3 cmp ebx 0xa0200000 4 jlge 0 Object4 if (getHeader(src) 5.and(LOGGING_MASK) 6.EQ(UNLOGGED)) 7 rememberObject(src); 1 lwz R4,-8(R5) 2 rlinm R4,R4,0x0,0x1d,0x1d 3 cmpiW cr1,R4,0x4 4 beq 1 78 1 mov ecx -8[edx] 2 and ecx 4 3 cmp ecx 4 4 jeq 0 Card4 int card=src.rshl(LOG_CARD_SIZE); 5 cardTable.add(card).store((byte) 1); 1 lwz R5,0x1664(JT) 2 rlinm R6,R3,0x16,0xa,0x1f 3 lil R7,0x1 4 stbx R7,R5,R6 1 mov ebx [0x290279a] 2 shr eax 10 3 mov [0+ebx+eax<<0] 1 Zone4 if (slot.xor(tgt).GE(ZONE_SIZE)) 5 remSlots.insert(slot); 1 xor R3,R30,R31 2 liu R5,0x40 3 cmplW cr1,R3,R5 4 bge 1 74 1 mov edi eax 2 mov eax edi 3 xor eax ebx 4 cmp eax 0x400000 5 jlge 0

8 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Experiments: Hardware 3 platforms: –1.9GHz AMD Athlon XP 2600 1GB –2.6GHz Pentium 4 1GB –1.6GHz PowerPC 970 768MB AMD and Intel performance counters –cycles –instructions retired –L1/L2 cache misses –TLB misses –both mutator and collector, separately

9 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Experiments: Software MMTk in Jikes RVM version 2.3.2+CVS –ignore remsets GC configuration (now in MMTk) –patched to support performance counters –pseudo-adaptive compilation –read barriers Debian Linux 2.6.0 kernel + x86 perfctr Standalone mode

10 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Write Barrier Overhead mean of SPECjvm98 & SPECjbb

11 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Write Barrier Code (Again) JavaPPC asmx86 asm Boundary (Slot) 4 if (slot.LT(NURSERY_START) 5 && tgt.GE(NURSERY_START)) 6 remSlots.insert(slot); 1 liu R3,0x6e10 2 cmplW cr1,R30,R3 3 bge 1 54 4 liu R3,0x6e10 5 cmplW cr1,R31,R3 6 bge 1 7c 1 cmp edi 0xa0200000 2 jlge 0 3 cmp ebx 0xa0200000 4 jlge 0 Object4 if (getHeader(src) 5.and(LOGGING_MASK) 6.EQ(UNLOGGED)) 7 rememberObject(src); 1 lwz R4,-8(R5) 2 rlinm R4,R4,0x0,0x1d,0x1d 3 cmpiW cr1,R4,0x4 4 beq 1 78 1 mov ecx -8[edx] 2 and ecx 4 3 cmp ecx 4 4 jeq 0 Card4 int card=src.rshl(LOG_CARD_SIZE); 5 cardTable.add(card).store((byte) 1); 1 lwz R5,0x1664(JT) 2 rlinm R6,R3,0x16,0xa,0x1f 3 lil R7,0x1 4 stbx R7,R5,R6 1 mov ebx [0x290279a] 2 shr eax 10 3 mov [0+ebx+eax<<0] 1 Zone4 if (slot.xor(tgt).GE(ZONE_SIZE)) 5 remSlots.insert(slot); 1 xor R3,R30,R31 2 liu R5,0x40 3 cmplW cr1,R3,R5 4 bge 1 74 1 mov edi eax 2 mov eax edi 3 xor eax ebx 4 cmp eax 0x400000 5 jlge 0

12 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Write Barrier Code (Again) JavaPPC asmx86 asm Boundary (Slot) 4 if (slot.LT(NURSERY_START) 5 && tgt.GE(NURSERY_START)) 6 remSlots.insert(slot); 1 liu R3,0x6e10 2 cmplW cr1,R30,R3 3 bge 1 54 4 liu R3,0x6e10 5 cmplW cr1,R31,R3 6 bge 1 7c 1 cmp edi 0xa0200000 2 jlge 0 3 cmp ebx 0xa0200000 4 jlge 0 Object4 if (getHeader(src) 5.and(LOGGING_MASK) 6.EQ(UNLOGGED)) 7 rememberObject(src); 1 lwz R4,-8(R5) 2 rlinm R4,R4,0x0,0x1d,0x1d 3 cmpiW cr1,R4,0x4 4 beq 1 78 1 mov ecx -8[edx] 2 and ecx 4 3 cmp ecx 4 4 jeq 0 Card4 int card=src.rshl(LOG_CARD_SIZE); 5 cardTable.add(card).store((byte) 1); 1 lwz R5,0x1664(JT) 2 rlinm R6,R3,0x16,0xa,0x1f 3 lil R7,0x1 4 stbx R7,R5,R6 1 mov ebx [0x290279a] 2 shr eax 10 3 mov [0+ebx+eax<<0] 1 Zone4 if (slot.xor(tgt).GE(ZONE_SIZE)) 5 remSlots.insert(slot); 1 xor R3,R30,R31 2 liu R5,0x40 3 cmplW cr1,R3,R5 4 bge 1 74 1 mov edi eax 2 mov eax edi 3 xor eax ebx 4 cmp eax 0x400000 5 jlge 0

13 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Write Barrier Code (Again) JavaPPC asmx86 asm Boundary (Slot) 4 if (slot.LT(NURSERY_START) 5 && tgt.GE(NURSERY_START)) 6 remSlots.insert(slot); 1 liu R3,0x6e10 2 cmplW cr1,R30,R3 3 bge 1 54 4 liu R3,0x6e10 5 cmplW cr1,R31,R3 6 bge 1 7c 1 cmp edi 0xa0200000 2 jlge 0 3 cmp ebx 0xa0200000 4 jlge 0 Object4 if (getHeader(src) 5.and(LOGGING_MASK) 6.EQ(UNLOGGED)) 7 rememberObject(src); 1 lwz R4,-8(R5) 2 rlinm R4,R4,0x0,0x1d,0x1d 3 cmpiW cr1,R4,0x4 4 beq 1 78 1 mov ecx -8[edx] 2 and ecx 4 3 cmp ecx 4 4 jeq 0 Card4 int card=src.rshl(LOG_CARD_SIZE); 5 cardTable.add(card).store((byte) 1); 1 lwz R5,0x1664(JT) 2 rlinm R6,R3,0x16,0xa,0x1f 3 lil R7,0x1 4 stbx R7,R5,R6 1 mov ebx [0x290279a] 2 shr eax 10 3 mov [0+ebx+eax<<0] 1 Zone4 if (slot.xor(tgt).GE(ZONE_SIZE)) 5 remSlots.insert(slot); 1 xor R3,R30,R31 2 liu R5,0x40 3 cmplW cr1,R3,R5 4 bge 1 74 1 mov edi eax 2 mov eax edi 3 xor eax ebx 4 cmp eax 0x400000 5 jlge 0

14 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 AMD Athlon 2600+ 1.9GHz Write Barrier

15 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Intel P4 2.6GHz Write Barrier

16 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 G5 PowerPC 970 1.6GHz Write Barrier

17 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Performance Counters

18 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Intel P4 2.6GHz Write Barrier Retired Instructions

19 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Intel P4 2.6GHz Write Barrier L1 Misses

20 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Intel P4 2.6GHz Write Barrier L2 Misses

21 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Intel P4 2.6GHz Write Barrier DTLB Misses

22 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Read Barrier Code 1 public final ObjectReference readBarrier(ObjectReference obj, 2 Address slot, int mode) 3 throws InlinePragma { 4 ObjectReference value = slot.loadObjectReference(); 5 return value; // insert read barrier code here 6}

23 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Read Barrier Code cont. JavaPPC asmx86 asm Unconditional5 return value.and(~3);1 rlinm R3,R3,0x0,0x0,0x1d1 and cax -4 Conditional5 if (value.and(1).NE(1)) 6 return value; 7 else 8 return 0; 1 rlinm R4,R3,0x0,0x1f,0x1f 2 cmpiW cr1,R4,0x1 3 bne 1 3c 1 mov edx eax 2 and edx 1 3 cmp edx 1 4 mov edx 0 5 cmovne edx eax 6 mov eax edx

24 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Read Barrier Overhead mean of SPECjvm98 & SPECjbb

25 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 AMD Athlon 2600+ 1.9GHz Read Barrier

26 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Intel P4 2.6GHz Read Barrier

27 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 G5 PowerPC 970 1.6GHz Read Barrier

28 Monday, June 02, 2014 International Symposium on Memory Management Vancouver BC, October 2004 Conclusions New methodology: available in MMTk –Specific barrier patches at: http://cs.anu.edu.au/~Steve.Blackburn/pubs/wb-ismm-2004.tgz Barrier costs (often) surprisingly low Barrier costs very architecturally sensitive –GC developers: think about your target arch. –GC papers: what architecture did they use? –Architects: choices impact OO languages in surprising ways.


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