2Learning Objectives To introduce analog and digital system Combinational circuitIdentify the basic gates and describe the behavior of eachCombine basic gates into circuitsAddersMultiplexer and de multiplexerEncoder and decoderSequential circuitLatch and flip flopTypes of flip flop
3Analog and DigitalTo be transmitted, data must be transformed to electromagnetic signals.Data can be analog or digital.The term analog data refers to information that iscontinuous; digital data refers to information that has discrete states.
4Analog and Digital Data and Signal Data can be analog or digital.Analog data are continuous and take continuous values.Digital data have discrete states and take discrete values.Signals can be analog or digital.Analog signals can have an infinite number of values in a range.Digital signals can have only a limited number of values.
6Digital ElectronicsDigital Electronics represents information (0, 1) with only two discrete values.Ideally “no voltage” (e.g., 0v) represents a 0 and “full source voltage” (e.g., 5v) represents a 1Realistically “low voltage” (e.g., <1v) represents a 0 and “high voltage” (e.g., >4v) represents a 1We achieve these discrete values by using switches.We use transistor switches, which operates at high speed, electronically, a small in size.
7Electronic Aspects of Digital Design How we represent digital information in electronic devices?By discrete voltages.
8What is the Basic Digital Element in Electronics ? a Switch
10Digital AbstractionIt is difficult to make ideal switches means a switch is completely ON or completely OFF.So, we impose some rules that allow analog behavior to be ignored in most cases, so circuits can be modeled as if they really did process 0s and 1s, known as digital abstraction.Digital abstraction allows us to associate a noise margin with each logic values (0 and 1).
11Logic levels Undefined region is inherent digital, not analog Switching threshold varies with voltage, tempneed “noise margin”Logic voltage levels decreasing with new processors.5 , 3.3 , 2.5 , 1.8 V
12Analog versus DigitalAnalog systems process time-varying signals that can take on any value across a continuous range of voltages (in electrical/electronics systems).Digital systems process time-varying signals that can take on only one of two discrete values of voltages (in electrical/electronics systems).Discrete values are called 1 and 0 (ON and OFF, HIGH and LOW, TRUE and FALSE, etc.)
13Representing Information Electronically “Analog electronics” deals with non-discrete values“Digital electronics” deals with discrete values
14Benefits of Digital over Analog ReproducibilityNot effected by noise means qualityEase of designData protectionProgrammableSpeedEconomy
15Digital systems started back in 1940s. Digital RevolutionDigital systems started back in 1940s.Digital systems cover all areas of life:still picturesdigital videodigital audiotelephonetraffic lightsAnimation
16Basic terminology Gate A device that performs a basic operation on electrical signalsCircuitsGates combined to perform more complicated tasksHow do we describe the behavior of gates and circuits?Boolean expressionsUses Boolean algebra, a mathematical notation for expressing two-valued logicLogic diagramsA graphical representation of a circuit; each gate has its own symbolTruth tablesA table showing all possible input value and the associated outputvalues
17Circuits can be Combinational or Sequential Combinational logic circuits produce a specified output (almost) at the instant when input values are applied.The addition of a memory device to a combinational circuit allows the output to be fed back into the input: Sequential circuitCombinational circuitcircuitmemoryInput(s)Output(s)Sequential circuit
20Overview Gates Iterative combinational circuits Binary adders Half and full addersRipple carryBinary subtractionBinary adder-subtractorsSigned binary numbersSigned binary addition and subtractionOverflow
21Combinational Circuits Combinational logic circuits produce a specified output (almost) at the instant when input values are applied.21
22GatesThe most basic digital devices are called gates.Gates got their name from their function of allowing or blocking (gating) the flow of digital information.A gate has one or more inputs and produces an output depending on the input(s).A gate is called a combinational circuit.Three most important gates are: AND, OR, NOT
23Binary system -- 0 & 1, LOW & HIGH, negated and asserted. Digital LogicBinary system -- 0 & 1, LOW & HIGH, negated and asserted.Basic building blocks -- AND, OR, NOT
24NOT GateA NOT gate accepts one input signal (0 or 1) and returns the opposite signal as output
25AND Gate An AND gate accepts two input signals If both are 1, the output is 1; otherwise the output is 0
26OR Gate An OR gate accepts two input signals If both are 0, the output is 0; otherwise, the output is 1
27XOR Gate An XOR gate accepts two input signals If both are the same, the output is 0; otherwise, the output is 1
28XOR Gate Note the difference between the XOR gate and the OR gate; they differ only in one input situationWhen both input signals are 1, the OR gate produces a1 and the XOR produces a 0XOR is called the exclusive OR
29NAND Gate The NAND gate accepts two input signals If both are 1, the output is 0; otherwise, the output is 1
30NOR Gate The NOR gate accepts two input signals If both are 0, the output is 1; otherwise, the output is 0
31De Morgan again A NAND gate: Y = A.B = A + B is the same as an OR gate with two NOT gatesSimilarly a NOR gate is the same as an AND gate with two invertersY = A + B = A.B
33Truth Tables and Boolean Notation NAND Gate RepresentationIt is possible to implement any boolean expression using only NAND gatesNOTXXANDA.BAA.BBORAA+BB
34Truth Tables and Boolean Notation NAND Gate representationImplement the following circuit using only NAND gatesx2x4x3
35Solution Dual the gates, remember two nots together can be removed. A.BAA.BBA+BBAND feeding ORx3x2x4
36Exercise Implement NOT, AND and OR using NOR gates Example AND gate dual circuit:
37Solution Similar pattern to using NAND gates (not surprising) NOT AND ORXXXA.BAAA.BBA.BBAA+BA.BAA+BBB
38Logic GatesNAND and NOR are known as universal gates because they are inexpensive to manufacture and any Boolean function can be constructed using only NAND or only NOR gates.38
39Truth Tables and Boolean Notation NOR Gate representationIt is also possible to implement any boolean expression using only NOR gatesImplement the following circuit using only NOR gatesX4X3X2
40Solution Two NOR gates in sequence acting as NOT’s can be eliminated: X4X3X2
41Logic Gates Gates can have multiple inputs and more than one output. A second output can be provided for the complement of the operation.41
42Conclusion Computers are implementations of Boolean logic. Boolean functions are completely described by truth tables.Logic gates are small circuits that implement Boolean operators.The basic gates are AND, OR, and NOT.The XOR gate is very useful in parity checkers and adders.The “universal gates” are NOR, and NAND.42
44Iterative Combinational Circuits Arithmetic functionsOperate on binary vectorsUse the same subfunction in each bit positionCan design functional block for subfunction and repeat to obtain functional block for overall functionCell - subfunction blockIterative array - a array of interconnected cellsAn iterative array can be in a single dimension (1D) or multiple dimensions
45Block Diagram of a 1D Iterative Array Example: n = 32Number of inputs = ?Truth table rows = ?Equations with up to ? input variablesEquations with huge number of termsDesign impractical!Iterative array takes advantage of the regularity to make design feasibleNumber of Inputs = 66Truth Table Rows = 266Equations with up to 66 variables
46Functional Blocks: Addition Binary addition used frequentlyAddition Development:Half-Adder (HA), a 2-input bit-wise addition functional block,Full-Adder (FA), a 3-input bit-wise addition functional block,Ripple Carry Adder, an iterative array to perform binary addition, andCarry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance. *(Details not required)
47Functional Block: Half-Adder A 2-input, 1-bit width binary adder that performs the following computations:A half adder adds two bits to produce a two-bit sumThe sum is expressed as a sum bit , S and a carry bit, CThe half adder can be specified as a truth table for S and C XYCS1X1+ Y+ 0+ 1C S0 00 11 0
48Logic Simplification: Half-Adder The K-Map for S, C is:This is a pretty trivial map! By inspection:andThese equations lead to several implementations. YX132SC)YX(S+×=Å)(CYX×=
49Five Implementations: Half-Adder We can derive following sets of equations for a half-adder:(a), (b), and (e) are SOP, POS, and XOR implementations for S.In (c), the C function is used as a term in the AND-NOR implementation of S, and in (d), the function is used in a POS term for S.YXC)(Scba×=+YXCS)e(d×=Å+C
50Implementations: Half-Adder The most common half adder implementation is: (e)A NAND only implementation is:XYCSYXCS×=ÅXYCS)(CYXS×=+
51Functional Block: Full-Adder A full adder is similar to a half adder, but includes a carry- in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C.For a carry-in (Z) of , it is the same as the half-adder:For a carry- in (Z) of 1:ZX1+ Y+ 0+ 1C S0 11 0Z1X+ Y+ 0+ 1C S0 11 0
52Logic Optimization: Full-Adder Full-Adder Truth Table:Full-Adder K-Map:XYZCS1SYCY111132132X11X11145764576ZZ
53Equations: Full-Adder From the K-Map, we get:The S function is the three-bit XOR function (Odd Function):The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or if the sum is 1 and a carry-in (Z) occurs. Thus C can be re-written as:The term X·Y is carry generate.The term XY is carry propagate.ZYXCS+=ZYXSÅ=Z)YX(CÅ+=
55Implementation: Full Adder AiBiCiCi+1GiPiSiFull Adder SchematicHere X, Y, and Z, and C (from the previous pages) are A, B, Ci and Co, respectively. Also, G = generate and P = propagate.Note: This is really a combination of a 3-bit odd function (for S)) and Carry logic (for Co): (G = Generate) OR (P =Propagate AND Ci = Carry In)Co = G + P · Ci
56Binary AddersTo add multiple operands, we “bundle” logical signals together into vectors and use functional blocks that operate on the vectorsExample: 4-bit ripple carry adder: Adds input vectors A(3:0) and B(3:0) to get a sum vector S(3:0)Note: carry out of cell i becomes carry in of cell i + 1DescriptionSubscriptNameCarry InCiAugendAiAddendBiSumSiCarry outCi+1
57Combinational Circuits Just as we combined half adders to make a full adder, full adders can connected in series.The carry bit “ripples” from one adder to the next; hence, this configuration is called a ripple-carry adder.Today’s systems employ more efficient adders.57
584-bit Ripple-Carry Binary Adder A four-bit Ripple Carry Adder made from four 1-bit Full Adders:
59Signed Integer Representations Signed-Magnitude – here the n – 1 digits are interpreted as a positive magnitude.Signed-Complement – here the digits are interpreted as the rest of the complement of the number. There are two possibilities here:Signed 1's ComplementUses 1's Complement ArithmeticSigned 2's ComplementUses 2's Complement Arithmetic
60Signed IntegersPositive numbers and zero can be represented by unsigned n-digit, radix r numbers. We need a representation for negative numbers.To represent a sign (+ or –) we need exactly one more bit of information (1 binary digit gives 21 = 2 elements which is exactly what is needed).Since computers use binary numbers, by convention, the most significant bit is interpreted as a sign bit:s an–2 a2a1a0 where: s = 0 for Positive numbers s = 1 for Negative numbers and ai = 0 or 1 represent the magnitude in some form.
61Signed-Magnitude Arithmetic If the parity of the three signs is 0:1. Add the magnitudes.2. Check for overflow (a carry out of the MSB)3. The sign of the result is the same as the sign of the first operand.If the parity of the three signs is 1:1. Subtract the second magnitude from the first.2. If a borrow occurs:take the two’s complement of resultand make the result sign the complement of the sign of the first operand.3. Overflow will never occur.
622’s Complement MethodGiven: an n-bit binary number, beginning at the least significant bit and proceeding upward:Copy all least significant 0’sCopy the first 1Complement all bits thereafter.2’s Complement Example:Copy underlined bits:100and complement bits to the left:
63Signed Integer Representation Example NumberSign-Mag.1's Comp.2's Comp.+3011+2010+1001+0000–100111—1101110234
64Signed-Complement Arithmetic Addition:1. Add the numbers including the sign bits, discarding a carry out of the sign bits (2's Complement), or using an end-around carry (1's Complement).2. If the sign bits were the same for both numbers and the sign of the result is different, an overflow has occurred.3. The sign of the result is computed in step 1.Subtraction:Form the complement of the number you are subtracting and follow the rules for addition.
652’s Complement Adder/Subtractor Subtraction can be done by addition of the 2's Complement.1. Complement each bit (1's Complement.)2. Add 1 to the result.The circuit shown computes A + B and A – B:For S = 1, subtract, the 2’s complement of B is formed by using XORs to form the 1’s comp and adding the 1 applied to C0.For S = 0, add, B is passed through unchanged
66Overflow DetectionOverflow occurs if n + 1 bits are required to contain the result from an n-bit addition or subtractionOverflow can occur for:Addition of two operands with the same signSubtraction of operands with different signsSigned number overflow cases with correct result signDetection can be performed by examining the result signs which should match the signs of the top operand
67Overflow DetectionSigned number cases with carries Cn and Cn-1 shown for correct result signs:Signed number cases with carries shown for erroneous result signs (indicating overflow):Simplest way to implement overflow V = Cn + Cn - 1This works correctly only if 1’s complement and the addition of the carry in of 1 is used to implement the complementation! Otherwise fails for
68Other Arithmetic Functions Convenient to design the functional blocks by contraction - removal of redundancy from circuit to which input fixing has been appliedFunctionsIncrementingDecrementingMultiplication by ConstantDivision by Constant
69Incrementing & Decrementing Adding a fixed value to an arithmetic variableFixed value is often 1, called counting (up)Examples: A + 1, B + 4Functional block is called incrementerDecrementingSubtracting a fixed value from an arithmetic variableFixed value is often 1, called counting (down)Examples: A - 1, B - 4Functional block is called decrementer
70Multiplication/Division by 2n (a) Multiplication by 100Shift left by 2(b) Division by 100Shift right by 2Remainder preservedB123C45(a)B123C(b)
71Combinational Circuits A multiplexer does just the opposite of a decoder.It selects a single output from several inputs.The particular input chosen for output is determined by the value of the multiplexer’s control lines.To be able to select among n inputs, log2n control lines are needed.This is a block diagram for a multiplexer.71
72Example of a Combinatorial Circuit: A Multiplexer (MUX) Consider an integer ‘m’, which isconstrained by the following relation:m = 2n, where m and n are both integers.A m-to-1 Multiplexer hasm Inputs: I0, I1, I2, I(m-1)one Output: Yn Control inputs: S0, S1, S2, S(n-1)One (or more) Enable input(s)such that Y may be equal to one of the inputs, depending upon the control inputs.
73Examples The Multiplexer Selects one of 2n inputs and copies it to a single outputThe selected line is determined from the bit combination (address) on the n selection linese.g. 1 from 2 mutiplexern = 1aout0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1sel a b outb1selsel a b outsel ab00011110A BC00011110111111out = not(sel).a + sel.bout =
74K map for 2:1 Multiplexer AB sel 00 01 11 10 1 output = sel.a + sel.b 1output = sel.a + sel.bdataPrincipal can be extended to4:1 – 2 select lines and 4 data lines8:1 – 3 select lines and 8 data linesand so on…outsel
752:1 Multiplexer sel a b out ? 1 sel a b out 1 AB sel 00 01 11 10 1 ?1selabout1if a is selected, don’t care about b.ABsel000111101
76Combinational Circuits This is what a 4-to-1 multiplexer looks like on the inside.If S0 = 1 and S1 = 0, which input is transferred to the output?76
77Demultiplexer (DMUX)/ Decoder A 1-to-m DMUX, with ACTIVE HIGH Outputs, has1 Input: I ( also called as the Enable input when the device is called a Decoder)m ACTIVE HIGH Outputs: Y0, Y1, Y2, …………….Y(m-1)n Control inputs: S0, S1, S2, S(m-1)
78Characteristic table of the 1-to-4 DMUX with ACTIVE HIGH Outputs:
79Characteristic Table of a 1-to-4 DMUX, with ACTIVE LOW Outputs:
80The diagram below shows the relation between a multiplexer and a Demultiplexer. S1 S0Y outY0Y1Y2Y4Input4 to 1MUX1 to 4DEMUX
81Combinational Circuits Decoders are another important type of combinational circuit.Among other things, they are useful in selecting a memory location according a binary value placed on the address lines of a memory bus.Address decoders with n inputs can select any of 2n locations.This is a block diagram for a decoder.81
82Combinational Circuits This is what a 2-to-4 decoder looks like on the inside.If x = 0 and y = 1, which output line is enabled?82
83A Decoder is a Demultiplexer with a change in the name of the inputs : Y0Y1Y2Y4S S0ENABLEINPUT2 to 4DecoderWhen the IC is used as a Decoder, the input I is called an Enable input
84DECODERThe ‘unexcited’ state of an Output is 0 for an IC with ACTIVE HIGH Outputs.The ‘unexcited’ state of an Output is 1 for an IC with ACTIVE LOW Outputs.Enable Input:In a Decoder, the Enable Input can be ACTIVE LOW or ACTIVE HIGH.
85Characteristic Table of a 2-to-4 DECODER, with ACTIVE LOW Outputs and with ACTIVE LOW Enable Input: Logic expressions for the outputs of the Decoder of Table:Y0 = E + S1 + S Y1 = E + S1+ S0‘Y2 = E + S1‘ + S Y3 = E + S1‘ + S0‘
86Encoders Multiple-input/multiple-output device. Performs the inverse function of a Decoder.Outputs ( m ) are less than inputs ( n ).Converts input code words into output code words.input codeoutput codeENCODER
88Encoder/Decoder Vocabulary ENCODER- a digital circuit that produces a binary output code depending on which of its inputs are activated.DECODER- a digital circuit that converts an input binary code into a single numeric output.
89ENCODERS AND DECODERS ONLY ONE INPUT ACTIVATED AT A TIME BINARY CODE INPUTONLY ONE OUTPUT ACTIVATED AT A TIMEBINARY CODE OUTPUT
90Binary Encoder 2^n-to-n encoder : 2^n inputs and n outputs. Input code : 1-out-of-2^n.Output code : Binary CodeExample : n=3, 8-to-3 encoder Inputs OutputsI0 I I2 I I4 I5 I I Y2 Y1 YI0I1I2Y0I3Y1I4Y2I5I6I7
918-to-3 encoder Implementation Simplified implementation: - From the truth table Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7Limitations : - I0 has no effect on the output - Only one input can be activatedApplication: Handling multiple devices requests But, no simultaneous requestsEstablishing priorities solve the problem of multiple requestsI1I2I3I4I5I6I0I7Y2Y1Y0
92What you should be able to do: Change circuits using one set of gates (e.g. AND, OR, NOT)to their equivalent using NAND or NOR gates only (and viceversa).Be familiar with half-, full- adders and multiplexer, demultiplexer, encoder and decoder circuits.
93TESTANSWER THE FOLLOWING QUESTIONS WITH ONE OR MORE OF THESE WORDS: MUX, DEMUX, ENCODER, DECODER.A. Has more inputs than outputs.ENCODER, MUXB. Uses select inputs.MUX, DEMUXC. Can be used in parallel-to-serial conversion.MUXD. Produces a binary code at its output.ENCODERE. Only one of its outputs is activated at one time.DEMUX, DECODERF. Used to route input signals to one of several outputs.MUXG. Used to generate arbitrary logic functions.MUX, DEMUXH. 3 line-to-8 line or binary to octal.DECODERI. Data Selectors are alsoMUX.
95Sequential Logic Circuits So far we have only considered circuits where the output is purely a function of the inputsWith sequential circuits the output is a function of the values of past and present inputs This particular example is not very useful173X = X + AExamples of sequential circuitsA counter to count the number of times a signal has changedA traffic light controller (remembering where it is up to in the sequence)
96Sequential CircuitsCombinational logic circuits are perfect for situations when we require the immediate application of a Boolean function to a set of inputs.There are other times, however, when we need a circuit to change its value with consideration to its current state as well as its inputs.These circuits have to “remember” their current state.Sequential logic circuits provide this functionality for us.96
97Integrated CircuitsA collection of one or more gates fabricated on a single silicon chip is called an integrated circuit (IC).ICs were classified by size:SSI - small scale integration - 1~20 gatesMSI - medium scale integration - 20~200 gatesLSI - large scale integration - 200~200,000 gatesVLSI - very large scale integration - over 1M transistorsPentium-III - 40 million transistors
98Sequential circuit concepts The addition of a memory device to a combinational circuit allowsthe output to be fed back into the input:To retain their state values, sequential circuits rely on feedback.Feedback in digital circuits occurs when an output is looped back tothe input.circuitInput(s)Output(s)memory
99Synchronous and Asynchronous circuitInput(s)Output(s)memoryClock pulseWith synchronous circuits a clock pulse is used to regulatethe feedback, input signal only enabled when clock pulse ishigh – acts like a “gate” being opened.
100Sequential CircuitsAs the name implies, sequential logic circuits require a means by which events can be sequenced.State changes are controlled by clocks.A “clock” is a special circuit that sends electrical pulses through a circuit.Clocks produce electrical waveforms such as the one shown below.100
101Sequential CircuitsState changes occur in sequential circuits only when the clock ticks.Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage.101
102Sequential CircuitsCircuits that change state on the rising edge, or falling edge of the clock pulse are called edge-triggered.Level-triggered circuits change state when the clock voltage reaches its highest or lowest level.102
103Clock Pulse Definition Positive PulsePositiveEdgeNegativeNegative PulsePositiveEdgeNegativeEdges can also be referred to as leading and trailing.
104Flip-flops A device that stores either a 0 or 1. Stored value can be changed only at certain times determined by a clock input.New value depend on the current state and it’s control inputsA digital circuit that contains filp-flops is called a sequential circuit
106LatchesTwo cross-coupled NOR gates form an SR (set and reset) latch
107Latches The SR Latch Consider the following circuit 1 R S Q Symbol R Q RSQSymbolRQSQCircuitR S Qn+10 0 Qn0 1 11 0 01 1 ?n+1 represents output at some future timeFunction Tablen represents current output.Although SR LAtch is one of the most important fundamental methods of didgital storage,it is not often used in practice (because of undefined state) - However forms the basis of the more complex latches that we will be dicussing
108SR Latch operation Assume some previous operation has Q as a 1 Assume R and S are initially inactiveIndicates a stable state at some future time (n+ = now plus)R = 0Q = 1R S Qn+10 0 Qn0 1 11 0 01 1 ?~Q = Q, ie is the complement of Q.S = 0Q = 0CircuitNow assume R goes first to 1 then returns to 0, what happens:
109Reset goes activeR = 1When R goes active 1, the output from the first gate must be 0.Q = 0This 0 feedsback to gate 2S = 0~Q = 1Since both inputs are 0 the output is forced to 1The output ~Q is fed back to gate 1, both inputs being 1 the output Q stays at 0.R = 1Q = 0S = 0~Q = 1
110Reset goes in-activeWhen R now goes in-active 0, the feedback from ~Q (still 1), holds Q at 0.R = 0Q = 0S = 0~Q = 1The “pulse” in R has changed the output as shown in the function table:R S Qn+10 0 Qn0 1 11 0 01 1 ?We went from hereTo hereAnd back againIn that process, Q changed from 1 to 0. Further signals on R will have no effect.
111Set the latchSimilar sequences can be followed to show that setting S to 1 then 0 – activating S – will set Q to a 1 stable state.When R and S are activated simultaneously both outputs will go to a 0R = 1Q = 0S = 1~Q = 0When R and S now go inactive 0, both inputs at both gatesare 0 and both gates output a 1.This 1 fedback to the inputs drives the outputs to 0, againboth inputs are 0 and so on and so on and so on and soon.
112Metastable stateIn a perfect world of perfect electronic circuits the oscillation continues indefinitely.However, delays will not be consistent in both gates so the circuit will collapse into one stable state or another.R S Qn+10 0 Qn0 1 11 0 01 1 ?This collapse is unpredictable.Thus our function table:Future output = present outputSet the latchReset the latchDon’t know
113Sequential Switching Elements R-S Latch RevisitedTruth Table:Next State = F(S, R, Current State)Derived K-Map:S(t)R(t)Q(t)Q(t+)10 HOLD0 RESET1 SETX Not AllowedXCharacteristic Equation:Q+ = S + R QtSR-SLatchRQ+Q
114Application of the SR Latch An important application of SR latches is for recording short lived eventse.g. pressing an alarm bell in a hospital
115Clocks and synchronization A clock is a special device that whose output continuously alternates between 0 and 1.The time it takes the clock to change from 1 to 0 and back to 1 is called the clock period, or clock cycle time.The clock frequency is the inverse of the clock period. The unit of measurement for frequency is the hertz.Clocks are often used to synchronize circuits.They generate a repeating, predictable pattern of 0s and 1s that can trigger certain events in a circuit, such as writing to a latch.If several circuits share a common clock signal, they can coordinate their actions with respect to one another.This is similar to how humans use real clocks for synchronization.clock period
116The Clocked SR LatchIn some cases it is necessary to disable the inputs to a latchThis can be achieved by adding a control or clock input to the latchWhen C = 0 R and S inputs cannot reach the latchHolds its stored valueWhen C = 1 R and S inputs connected to the latchFunctions as beforeSRQC
117Clocked SR Latch R S C Qn+1 X X 0 Qn Hold 0 0 1 Qn Hold 0 1 1 1 Set Reset1 1 1 ? UnusedRRQQCCSSQQ
118Clocked D LatchSimplest clocked latch of practical importance is the Clocked D latchDSQCQRIt means that both active 1 inputs at R and S can’t occur.Notice we’ve reversed S and R so when D is 1 Q is 1.
119D Latch D C Q It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its inputSymbols are often labeled data and enable/clock (D and C)DDCQSQQD C Qn+1X 0 Qn Hold0 1 0 Reset1 1 1 SetCCRQQCircuitSymbolFunction Table
120Transparency The devices that we have looked so far are transparent That is when C = 1 the output follows the inputThere will be a slight lag between them1CWhen the clock “gate” opens, changes in input take effect at outputs – transparency. Also known as “level-triggered”.t1DtAnalogous to:- opening a shutter to let light through a window (except when shutter closed light does not remain at level just before it closed)- Locks in a dam a better example1Qt1Ct1Dt1Qt
121Latches - SummaryTwo cross-coupled NOR gates form an SR (set and reset) latchA clocked SR latch has an additional input that controls when setting and resetting can take placeA D latch has a single data inputthe output is held when the clock input is a zerothe input is copied to the output when the clock input is a oneThe output of the clocked latches is transparentThe output of the clocked D latch can be represented by the following behaviorD C Qn+1X 0 Qn Hold0 1 0 Reset1 1 1 Set
122Latches and Flip Flops Terms are sometimes used confusingly: A latch is not clocked whereas a flip-flop is clocked.A clocked latch can therefore equally be referred to as a flip flop(SR flip flop, D flip flop).However, as we shall see, all practical flip flops are edge- triggeredon the clock pulse.Sometimes latches are included within flip flops as a sub-type.Clocked latches are level triggered. While the clock is high, inputsand thus outputs can change.This is not always desirable.A Flip Flop is edge-triggered – either by the leading or falling edgeof the clock pulse.Ideally, it responds to the inputs only at a particular instant in time.
123Computer Organization class Welcome toComputer Organization class