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**Introduction to Digital Electronics**

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**Learning Objectives To introduce analog and digital system**

Combinational circuit Identify the basic gates and describe the behavior of each Combine basic gates into circuits Adders Multiplexer and de multiplexer Encoder and decoder Sequential circuit Latch and flip flop Types of flip flop

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Analog and Digital To be transmitted, data must be transformed to electromagnetic signals. Data can be analog or digital. The term analog data refers to information that is continuous; digital data refers to information that has discrete states.

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**Analog and Digital Data and Signal**

Data can be analog or digital. Analog data are continuous and take continuous values. Digital data have discrete states and take discrete values. Signals can be analog or digital. Analog signals can have an infinite number of values in a range. Digital signals can have only a limited number of values.

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**Comparison of Analog and Digital Signals**

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Digital Electronics Digital Electronics represents information (0, 1) with only two discrete values. Ideally “no voltage” (e.g., 0v) represents a 0 and “full source voltage” (e.g., 5v) represents a 1 Realistically “low voltage” (e.g., <1v) represents a 0 and “high voltage” (e.g., >4v) represents a 1 We achieve these discrete values by using switches. We use transistor switches, which operates at high speed, electronically, a small in size.

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**Electronic Aspects of Digital Design**

How we represent digital information in electronic devices? By discrete voltages.

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**What is the Basic Digital Element in Electronics ?**

a Switch

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**Using Switch to Represent Digital Information**

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Digital Abstraction It is difficult to make ideal switches means a switch is completely ON or completely OFF. So, we impose some rules that allow analog behavior to be ignored in most cases, so circuits can be modeled as if they really did process 0s and 1s, known as digital abstraction. Digital abstraction allows us to associate a noise margin with each logic values (0 and 1).

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**Logic levels Undefined region is inherent digital, not analog**

Switching threshold varies with voltage, temp need “noise margin” Logic voltage levels decreasing with new processors. 5 , 3.3 , 2.5 , 1.8 V

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Analog versus Digital Analog systems process time-varying signals that can take on any value across a continuous range of voltages (in electrical/electronics systems). Digital systems process time-varying signals that can take on only one of two discrete values of voltages (in electrical/electronics systems). Discrete values are called 1 and 0 (ON and OFF, HIGH and LOW, TRUE and FALSE, etc.)

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**Representing Information Electronically**

“Analog electronics” deals with non-discrete values “Digital electronics” deals with discrete values

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**Benefits of Digital over Analog**

Reproducibility Not effected by noise means quality Ease of design Data protection Programmable Speed Economy

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**Digital systems started back in 1940s. **

Digital Revolution Digital systems started back in 1940s. Digital systems cover all areas of life: still pictures digital video digital audio telephone traffic lights Animation

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**Basic terminology Gate**

A device that performs a basic operation on electrical signals Circuits Gates combined to perform more complicated tasks How do we describe the behavior of gates and circuits? Boolean expressions Uses Boolean algebra, a mathematical notation for expressing two-valued logic Logic diagrams A graphical representation of a circuit; each gate has its own symbol Truth tables A table showing all possible input value and the associated output values

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**Circuits can be Combinational or Sequential**

Combinational logic circuits produce a specified output (almost) at the instant when input values are applied. The addition of a memory device to a combinational circuit allows the output to be fed back into the input: Sequential circuit Combinational circuit circuit memory Input(s) Output(s) Sequential circuit

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**Digital Devices Combinational circuit Sequential circuit Gates**

Multiplexer Demultiplexer Adders Encoder Decoder Sequential circuit Flip-Flops Registers Counters

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**Combinational Circuits**

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**Overview Gates Iterative combinational circuits Binary adders**

Half and full adders Ripple carry Binary subtraction Binary adder-subtractors Signed binary numbers Signed binary addition and subtraction Overflow

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**Combinational Circuits**

Combinational logic circuits produce a specified output (almost) at the instant when input values are applied. 21

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Gates The most basic digital devices are called gates. Gates got their name from their function of allowing or blocking (gating) the flow of digital information. A gate has one or more inputs and produces an output depending on the input(s). A gate is called a combinational circuit. Three most important gates are: AND, OR, NOT

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**Binary system -- 0 & 1, LOW & HIGH, negated and asserted. **

Digital Logic Binary system -- 0 & 1, LOW & HIGH, negated and asserted. Basic building blocks -- AND, OR, NOT

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NOT Gate A NOT gate accepts one input signal (0 or 1) and returns the o pposite signal as output

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**AND Gate An AND gate accepts two input signals**

If both are 1, the output is 1; otherwise the output is 0

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**OR Gate An OR gate accepts two input signals**

If both are 0, the output is 0; otherwise, the output is 1

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**XOR Gate An XOR gate accepts two input signals**

If both are the same, the output is 0; otherwise, the output is 1

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**XOR Gate Note the difference between the XOR gate and the OR**

gate; they differ only in one input situation When both input signals are 1, the OR gate produces a 1 and the XOR produces a 0 XOR is called the exclusive OR

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**NAND Gate The NAND gate accepts two input signals**

If both are 1, the output is 0; otherwise, the output is 1

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**NOR Gate The NOR gate accepts two input signals**

If both are 0, the output is 1; otherwise, the output is 0

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**De Morgan again A NAND gate: Y = A.B = A + B**

is the same as an OR gate with two NOT gates Similarly a NOR gate is the same as an AND gate with two inverters Y = A + B = A.B

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Dual gates

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**Truth Tables and Boolean Notation**

NAND Gate Representation It is possible to implement any boolean expression using only NAND gates NOT X X AND A.B A A.B B OR A A+B B

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**Truth Tables and Boolean Notation**

NAND Gate representation Implement the following circuit using only NAND gates x2 x4 x3

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**Solution Dual the gates, remember two nots together can be removed.**

A.B A A.B B A+B B AND feeding OR x3 x2 x4

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**Exercise Implement NOT, AND and OR using NOR gates**

Example AND gate dual circuit:

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**Solution Similar pattern to using NAND gates (not surprising) NOT AND**

OR X X X A.B A A A.B B A.B B A A+B A.B A A+B B B

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Logic Gates NAND and NOR are known as universal gates because they are inexpensive to manufacture and any Boolean function can be constructed using only NAND or only NOR gates. 38

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**Truth Tables and Boolean Notation**

NOR Gate representation It is also possible to implement any boolean expression using only NOR gates Implement the following circuit using only NOR gates X4 X3 X 2

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**Solution Two NOR gates in sequence acting as NOT’s can be eliminated:**

X4 X3 X 2

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**Logic Gates Gates can have multiple inputs and more than one output.**

A second output can be provided for the complement of the operation. 41

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**Conclusion Computers are implementations of Boolean logic.**

Boolean functions are completely described by truth tables. Logic gates are small circuits that implement Boolean operators. The basic gates are AND, OR, and NOT. The XOR gate is very useful in parity checkers and adders. The “universal gates” are NOR, and NAND. 42

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Implementation F=X.Y.+X’.Y’.Z

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**Iterative Combinational Circuits**

Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block for subfunction and repeat to obtain functional block for overall function Cell - subfunction block Iterative array - a array of interconnected cells An iterative array can be in a single dimension (1D) or multiple dimensions

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**Block Diagram of a 1D Iterative Array**

Example: n = 32 Number of inputs = ? Truth table rows = ? Equations with up to ? input variables Equations with huge number of terms Design impractical! Iterative array takes advantage of the regularity to make design feasible Number of Inputs = 66 Truth Table Rows = 266 Equations with up to 66 variables

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**Functional Blocks: Addition**

Binary addition used frequently Addition Development: Half-Adder (HA), a 2-input bit-wise addition functional block, Full-Adder (FA), a 3-input bit-wise addition functional block, Ripple Carry Adder, an iterative array to perform binary addition, and Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance. *(Details not required)

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**Functional Block: Half-Adder**

A 2-input, 1-bit width binary adder that performs the following computations: A half adder adds two bits to produce a two-bit sum The sum is expressed as a sum bit , S and a carry bit, C The half adder can be specified as a truth table for S and C X Y C S 1 X 1 + Y + 0 + 1 C S 0 0 0 1 1 0

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**Logic Simplification: Half-Adder**

The K-Map for S, C is: This is a pretty trivial map! By inspection: and These equations lead to several implementations. Y X 1 3 2 S C ) Y X ( S + × = Å ) ( C Y X × =

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**Five Implementations: Half-Adder**

We can derive following sets of equations for a half-adder: (a), (b), and (e) are SOP, POS, and XOR implementations for S. In (c), the C function is used as a term in the AND-NOR implementation of S, and in (d), the function is used in a POS term for S. Y X C ) ( S c b a × = + Y X C S ) e ( d × = Å + C

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**Implementations: Half-Adder**

The most common half adder implementation is: (e) A NAND only implementation is: X Y C S Y X C S × = Å X Y C S ) ( C Y X S × = +

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**Functional Block: Full-Adder**

A full adder is similar to a half adder, but includes a carry- in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. For a carry-in (Z) of , it is the same as the half-adder: For a carry- in (Z) of 1: Z X 1 + Y + 0 + 1 C S 0 1 1 0 Z 1 X + Y + 0 + 1 C S 0 1 1 0

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**Logic Optimization: Full-Adder**

Full-Adder Truth Table: Full-Adder K-Map: X Y Z C S 1 S Y C Y 1 1 1 1 3 2 1 3 2 X 1 1 X 1 1 1 4 5 7 6 4 5 7 6 Z Z

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**Equations: Full-Adder**

From the K-Map, we get: The S function is the three-bit XOR function (Odd Function): The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or if the sum is 1 and a carry-in (Z) occurs. Thus C can be re-written as: The term X·Y is carry generate. The term XY is carry propagate. Z Y X C S + = Z Y X S Å = Z ) Y X ( C Å + =

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Full Adder Circuit X Y Z=Cin Cout Sum

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**Implementation: Full Adder**

Ai Bi Ci Ci+1 Gi Pi Si Full Adder Schematic Here X, Y, and Z, and C (from the previous pages) are A, B, Ci and Co, respectively. Also, G = generate and P = propagate. Note: This is really a combination of a 3-bit odd function (for S)) and Carry logic (for Co): (G = Generate) OR (P =Propagate AND Ci = Carry In) Co = G + P · Ci

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Binary Adders To add multiple operands, we “bundle” logical signals together into vectors and use functional blocks that operate on the vectors Example: 4-bit ripple carry adder: Adds input vectors A(3:0) and B(3:0) to get a sum vector S(3:0) Note: carry out of cell i becomes carry in of cell i + 1 Description Subscript Name Carry In Ci Augend Ai Addend Bi Sum Si Carry out Ci+1

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**Combinational Circuits**

Just as we combined half adders to make a full adder, full adders can connected in series. The carry bit “ripples” from one adder to the next; hence, this configuration is called a ripple-carry adder. Today’s systems employ more efficient adders. 57

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**4-bit Ripple-Carry Binary Adder**

A four-bit Ripple Carry Adder made from four 1-bit Full Adders:

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**Signed Integer Representations**

Signed-Magnitude – here the n – 1 digits are interpreted as a positive magnitude. Signed-Complement – here the digits are interpreted as the rest of the complement of the number. There are two possibilities here: Signed 1's Complement Uses 1's Complement Arithmetic Signed 2's Complement Uses 2's Complement Arithmetic

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Signed Integers Positive numbers and zero can be represented by unsigned n-digit, radix r numbers. We need a representation for negative numbers. To represent a sign (+ or –) we need exactly one more bit of information (1 binary digit gives 21 = 2 elements which is exactly what is needed). Since computers use binary numbers, by convention, the most significant bit is interpreted as a sign bit: s an–2 a2a1a0 where: s = 0 for Positive numbers s = 1 for Negative numbers and ai = 0 or 1 represent the magnitude in some form.

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**Signed-Magnitude Arithmetic**

If the parity of the three signs is 0: 1. Add the magnitudes. 2. Check for overflow (a carry out of the MSB) 3. The sign of the result is the same as the sign of the first operand. If the parity of the three signs is 1: 1. Subtract the second magnitude from the first. 2. If a borrow occurs: take the two’s complement of result and make the result sign the complement of the sign of the first operand. 3. Overflow will never occur.

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2’s Complement Method Given: an n-bit binary number, beginning at the least significant bit and proceeding upward: Copy all least significant 0’s Copy the first 1 Complement all bits thereafter. 2’s Complement Example: Copy underlined bits: 100 and complement bits to the left:

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**Signed Integer Representation Example**

Number Sign - Mag. 1's Comp. 2's Comp. +3 011 +2 010 +1 001 +0 000 – 100 111 — 1 101 110 2 3 4

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**Signed-Complement Arithmetic**

Addition: 1. Add the numbers including the sign bits, discarding a carry out of the sign bits (2's Complement), or using an end-around carry (1's Complement). 2. If the sign bits were the same for both numbers and the sign of the result is different, an overflow has occurred. 3. The sign of the result is computed in step 1. Subtraction: Form the complement of the number you are subtracting and follow the rules for addition.

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**2’s Complement Adder/Subtractor**

Subtraction can be done by addition of the 2's Complement. 1. Complement each bit (1's Complement.) 2. Add 1 to the result. The circuit shown computes A + B and A – B: For S = 1, subtract, the 2’s complement of B is formed by using XORs to form the 1’s comp and adding the 1 applied to C0. For S = 0, add, B is passed through unchanged

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Overflow Detection Overflow occurs if n + 1 bits are required to contain the result from an n-bit addition or subtraction Overflow can occur for: Addition of two operands with the same sign Subtraction of operands with different signs Signed number overflow cases with correct result sign Detection can be performed by examining the result signs which should match the signs of the top operand

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Overflow Detection Signed number cases with carries Cn and Cn-1 shown for correct result signs: Signed number cases with carries shown for erroneous result signs (indicating overflow): Simplest way to implement overflow V = Cn + Cn - 1 This works correctly only if 1’s complement and the addition of the carry in of 1 is used to implement the complementation! Otherwise fails for

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**Other Arithmetic Functions**

Convenient to design the functional blocks by contraction - removal of redundancy from circuit to which input fixing has been applied Functions Incrementing Decrementing Multiplication by Constant Division by Constant

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**Incrementing & Decrementing**

Adding a fixed value to an arithmetic variable Fixed value is often 1, called counting (up) Examples: A + 1, B + 4 Functional block is called incrementer Decrementing Subtracting a fixed value from an arithmetic variable Fixed value is often 1, called counting (down) Examples: A - 1, B - 4 Functional block is called decrementer

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**Multiplication/Division by 2n**

(a) Multiplication by 100 Shift left by 2 (b) Division by 100 Shift right by 2 Remainder preserved B 1 2 3 C 4 5 (a) B 1 2 3 C (b)

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**Combinational Circuits**

A multiplexer does just the opposite of a decoder. It selects a single output from several inputs. The particular input chosen for output is determined by the value of the multiplexer’s control lines. To be able to select among n inputs, log2n control lines are needed. This is a block diagram for a multiplexer. 71

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**Example of a Combinatorial Circuit: A Multiplexer (MUX)**

Consider an integer ‘m’, which is constrained by the following relation: m = 2n, where m and n are both integers. A m-to-1 Multiplexer has m Inputs: I0, I1, I2, I(m-1) one Output: Y n Control inputs: S0, S1, S2, S(n-1) One (or more) Enable input(s) such that Y may be equal to one of the inputs, depending upon the control inputs.

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**Examples The Multiplexer**

Selects one of 2n inputs and copies it to a single output The selected line is determined from the bit combination (address) on the n selection lines e.g. 1 from 2 mutiplexer n = 1 a out 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 sel a b out b 1 sel sel a b out sel ab 00 01 11 10 A BC 00 01 11 10 1 1 1 1 1 1 out = not(sel).a + sel.b out =

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**K map for 2:1 Multiplexer AB sel 00 01 11 10 1 output = sel.a + sel.b**

1 output = sel.a + sel.b data Principal can be extended to 4:1 – 2 select lines and 4 data lines 8:1 – 3 select lines and 8 data lines and so on… out sel

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**2:1 Multiplexer sel a b out ? 1 sel a b out 1 AB sel 00 01 11 10 1**

? 1 sel a b out 1 if a is selected, don’t care about b. AB sel 00 01 11 10 1

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**Combinational Circuits**

This is what a 4-to-1 multiplexer looks like on the inside. If S0 = 1 and S1 = 0, which input is transferred to the output? 76

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**Demultiplexer (DMUX)/ Decoder**

A 1-to-m DMUX, with ACTIVE HIGH Outputs, has 1 Input: I ( also called as the Enable input when the device is called a Decoder) m ACTIVE HIGH Outputs: Y0, Y1, Y2, …………….Y(m-1) n Control inputs: S0, S1, S2, S(m-1)

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**Characteristic table of the 1-to-4 DMUX with ACTIVE HIGH Outputs:**

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**Characteristic Table of a 1-to-4 DMUX, with ACTIVE LOW Outputs:**

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**The diagram below shows the relation between a multiplexer and a Demultiplexer.**

S1 S0 Y out Y0 Y1 Y2 Y4 Input 4 to 1 MUX 1 to 4 DEMUX

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**Combinational Circuits**

Decoders are another important type of combinational circuit. Among other things, they are useful in selecting a memory location according a binary value placed on the address lines of a memory bus. Address decoders with n inputs can select any of 2n locations. This is a block diagram for a decoder. 81

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**Combinational Circuits**

This is what a 2-to-4 decoder looks like on the inside. If x = 0 and y = 1, which output line is enabled? 82

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**A Decoder is a Demultiplexer with a change in the name of the inputs :**

Y0 Y1 Y2 Y4 S S0 ENABLE INPUT 2 to 4 Decoder When the IC is used as a Decoder, the input I is called an Enable input

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DECODER The ‘unexcited’ state of an Output is 0 for an IC with ACTIVE HIGH Outputs. The ‘unexcited’ state of an Output is 1 for an IC with ACTIVE LOW Outputs. Enable Input: In a Decoder, the Enable Input can be ACTIVE LOW or ACTIVE HIGH.

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**Characteristic Table of a 2-to-4 DECODER, with ACTIVE LOW Outputs and with ACTIVE LOW Enable Input:**

Logic expressions for the outputs of the Decoder of Table: Y0 = E + S1 + S Y1 = E + S1+ S0‘ Y2 = E + S1‘ + S Y3 = E + S1‘ + S0‘

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**Encoders Multiple-input/multiple-output device.**

Performs the inverse function of a Decoder. Outputs ( m ) are less than inputs ( n ). Converts input code words into output code words. input code output code ENCODER

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**Binary decoders/encoders**

Encoders vs. Decoders Decoder Encoder Binary decoders/encoders n-to-2^n Input code : Binary Code Output code :1-out-of-2^n. 2^n-to-n encoder Input code : 1-out-of-2^n. Output code : Binary Code

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**Encoder/Decoder Vocabulary**

ENCODER- a digital circuit that produces a binary output code depending on which of its inputs are activated. DECODER- a digital circuit that converts an input binary code into a single numeric output.

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**ENCODERS AND DECODERS ONLY ONE INPUT ACTIVATED AT A TIME**

BINARY CODE INPUT ONLY ONE OUTPUT ACTIVATED AT A TIME BINARY CODE OUTPUT

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**Binary Encoder 2^n-to-n encoder : 2^n inputs and n outputs.**

Input code : 1-out-of-2^n. Output code : Binary Code Example : n=3, 8-to-3 encoder Inputs Outputs I0 I I2 I I4 I5 I I Y2 Y1 Y I0 I1 I2 Y0 I3 Y1 I4 Y2 I5 I6 I7

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**8-to-3 encoder Implementation**

Simplified implementation: - From the truth table Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7 Limitations : - I0 has no effect on the output - Only one input can be activated Application: Handling multiple devices requests But, no simultaneous requests Establishing priorities solve the problem of multiple requests I1 I2 I3 I4 I5 I6 I0 I7 Y2 Y1 Y0

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**What you should be able to do:**

Change circuits using one set of gates (e.g. AND, OR, NOT) to their equivalent using NAND or NOR gates only (and vice versa). Be familiar with half-, full- adders and multiplexer, de multiplexer, encoder and decoder circuits.

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TEST ANSWER THE FOLLOWING QUESTIONS WITH ONE OR MORE OF THESE WORDS: MUX, DEMUX, ENCODER, DECODER. A. Has more inputs than outputs. ENCODER, MUX B. Uses select inputs. MUX, DEMUX C. Can be used in parallel-to-serial conversion. MUX D. Produces a binary code at its output. ENCODER E. Only one of its outputs is activated at one time. DEMUX, DECODER F. Used to route input signals to one of several outputs. MUX G. Used to generate arbitrary logic functions. MUX, DEMUX H. 3 line-to-8 line or binary to octal. DECODER I. Data Selectors are also MUX.

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Sequential Logic

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**Sequential Logic Circuits**

So far we have only considered circuits where the output is purely a function of the inputs With sequential circuits the output is a function of the values of past and present inputs This particular example is not very useful 1 7 3 X = X + A Examples of sequential circuits A counter to count the number of times a signal has changed A traffic light controller (remembering where it is up to in the sequence)

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Sequential Circuits Combinational logic circuits are perfect for situations when we require the immediate application of a Boolean function to a set of inputs. There are other times, however, when we need a circuit to change its value with consideration to its current state as well as its inputs. These circuits have to “remember” their current state. Sequential logic circuits provide this functionality for us. 96

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Integrated Circuits A collection of one or more gates fabricated on a single silicon chip is called an integrated circuit (IC). ICs were classified by size: SSI - small scale integration - 1~20 gates MSI - medium scale integration - 20~200 gates LSI - large scale integration - 200~200,000 gates VLSI - very large scale integration - over 1M transistors Pentium-III - 40 million transistors

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**Sequential circuit concepts**

The addition of a memory device to a combinational circuit allows the output to be fed back into the input: To retain their state values, sequential circuits rely on feedback. Feedback in digital circuits occurs when an output is looped back to the input. circuit Input(s) Output(s) memory

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**Synchronous and Asynchronous**

circuit Input(s) Output(s) memory Clock pulse With synchronous circuits a clock pulse is used to regulate the feedback, input signal only enabled when clock pulse is high – acts like a “gate” being opened.

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Sequential Circuits As the name implies, sequential logic circuits require a means by which events can be sequenced. State changes are controlled by clocks. A “clock” is a special circuit that sends electrical pulses through a circuit. Clocks produce electrical waveforms such as the one shown below. 100

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Sequential Circuits State changes occur in sequential circuits only when the clock ticks. Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage. 101

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Sequential Circuits Circuits that change state on the rising edge, or falling edge of the clock pulse are called edge-triggered. Level-triggered circuits change state when the clock voltage reaches its highest or lowest level. 102

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**Clock Pulse Definition**

Positive Pulse Positive Edge Negative Negative Pulse Positive Edge Negative Edges can also be referred to as leading and trailing.

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**Flip-flops A device that stores either a 0 or 1.**

Stored value can be changed only at certain times determined by a clock input. New value depend on the current state and it’s control inputs A digital circuit that contains filp-flops is called a sequential circuit

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Flip-flops S-R latch symbols D flip-flop J-K flip-flops

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Latches Two cross-coupled NOR gates form an SR (set and reset) latch

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**Latches The SR Latch Consider the following circuit 1 R S Q Symbol R Q**

R S Q Symbol R Q S Q Circuit R S Qn+1 0 0 Qn 0 1 1 1 0 0 1 1 ? n+1 represents output at some future time Function Table n represents current output. Although SR LAtch is one of the most important fundamental methods of didgital storage,it is not often used in practice (because of undefined state) - However forms the basis of the more complex latches that we will be dicussing

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**SR Latch operation Assume some previous operation has Q as a 1**

Assume R and S are initially inactive Indicates a stable state at some future time (n+ = now plus) R = 0 Q = 1 R S Qn+1 0 0 Qn 0 1 1 1 0 0 1 1 ? ~Q = Q, ie is the complement of Q. S = 0 Q = 0 Circuit Now assume R goes first to 1 then returns to 0, what happens:

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Reset goes active R = 1 When R goes active 1, the output from the first gate must be 0. Q = 0 This 0 feeds back to gate 2 S = 0 ~Q = 1 Since both inputs are 0 the output is forced to 1 The output ~Q is fed back to gate 1, both inputs being 1 the output Q stays at 0. R = 1 Q = 0 S = 0 ~Q = 1

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Reset goes in-active When R now goes in-active 0, the feedback from ~Q (still 1), holds Q at 0. R = 0 Q = 0 S = 0 ~Q = 1 The “pulse” in R has changed the output as shown in the function table: R S Qn+1 0 0 Qn 0 1 1 1 0 0 1 1 ? We went from here To here And back again In that process, Q changed from 1 to 0. Further signals on R will have no effect.

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Set the latch Similar sequences can be followed to show that setting S to 1 then 0 – activating S – will set Q to a 1 stable state. When R and S are activated simultaneously both outputs will go to a 0 R = 1 Q = 0 S = 1 ~Q = 0 When R and S now go inactive 0, both inputs at both gates are 0 and both gates output a 1. This 1 fedback to the inputs drives the outputs to 0, again both inputs are 0 and so on and so on and so on and so on.

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Metastable state In a perfect world of perfect electronic circuits the oscillation continues indefinitely. However, delays will not be consistent in both gates so the circuit will collapse into one stable state or another. R S Qn+1 0 0 Qn 0 1 1 1 0 0 1 1 ? This collapse is unpredictable. Thus our function table: Future output = present output Set the latch Reset the latch Don’t know

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**Sequential Switching Elements**

R-S Latch Revisited Truth Table: Next State = F(S, R, Current State) Derived K-Map: S(t) R(t) Q(t) Q(t+) 1 0 HOLD 0 RESET 1 SET X Not Allowed X Characteristic Equation: Q+ = S + R Q t S R-S Latch R Q+ Q

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**Application of the SR Latch**

An important application of SR latches is for recording short lived events e.g. pressing an alarm bell in a hospital

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**Clocks and synchronization**

A clock is a special device that whose output continuously alternates between 0 and 1. The time it takes the clock to change from 1 to 0 and back to 1 is called the clock period, or clock cycle time. The clock frequency is the inverse of the clock period. The unit of measurement for frequency is the hertz. Clocks are often used to synchronize circuits. They generate a repeating, predictable pattern of 0s and 1s that can trigger certain events in a circuit, such as writing to a latch. If several circuits share a common clock signal, they can coordinate their actions with respect to one another. This is similar to how humans use real clocks for synchronization. clock period

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The Clocked SR Latch In some cases it is necessary to disable the inputs to a latch This can be achieved by adding a control or clock input to the latch When C = 0 R and S inputs cannot reach the latch Holds its stored value When C = 1 R and S inputs connected to the latch Functions as before S R Q C

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**Clocked SR Latch R S C Qn+1 X X 0 Qn Hold 0 0 1 Qn Hold 0 1 1 1 Set**

Reset 1 1 1 ? Unused R R Q Q C C S S Q Q

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Clocked D Latch Simplest clocked latch of practical importance is the Clocked D latch D S Q C Q R It means that both active 1 inputs at R and S can’t occur. Notice we’ve reversed S and R so when D is 1 Q is 1.

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**D Latch D C Q It removes the undefined behaviour of the SR latch**

Often used as a basic memory element for the short term storage of a binary digit applied to its input Symbols are often labeled data and enable/clock (D and C) D D C Q S Q Q D C Qn+1 X 0 Qn Hold 0 1 0 Reset 1 1 1 Set C C R Q Q Circuit Symbol Function Table

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**Transparency The devices that we have looked so far are transparent**

That is when C = 1 the output follows the input There will be a slight lag between them 1 C When the clock “gate” opens, changes in input take effect at outputs – transparency. Also known as “level-triggered”. t 1 D t Analogous to: - opening a shutter to let light through a window (except when shutter closed light does not remain at level just before it closed) - Locks in a dam a better example 1 Q t 1 C t 1 D t 1 Q t

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Latches - Summary Two cross-coupled NOR gates form an SR (set and reset) latch A clocked SR latch has an additional input that controls when setting and resetting can take place A D latch has a single data input the output is held when the clock input is a zero the input is copied to the output when the clock input is a one The output of the clocked latches is transparent The output of the clocked D latch can be represented by the following behavior D C Qn+1 X 0 Qn Hold 0 1 0 Reset 1 1 1 Set

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**Latches and Flip Flops Terms are sometimes used confusingly:**

A latch is not clocked whereas a flip-flop is clocked. A clocked latch can therefore equally be referred to as a flip flop (SR flip flop, D flip flop). However, as we shall see, all practical flip flops are edge- triggered on the clock pulse. Sometimes latches are included within flip flops as a sub-type. Clocked latches are level triggered. While the clock is high, inputs and thus outputs can change. This is not always desirable. A Flip Flop is edge-triggered – either by the leading or falling edge of the clock pulse. Ideally, it responds to the inputs only at a particular instant in time.

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**Computer Organization class**

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Sequential Logic Design

Sequential Logic Design

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