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16-bit RISC Microprocessor

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Presentation on theme: "16-bit RISC Microprocessor"— Presentation transcript:

1 16-bit RISC Microprocessor
Cecilia Florescu Mojdeh Makabi Daniel Yee December 2, 2002 CS M152B

2 Overview Purpose: Design a pipelined RISC microprocessor
Design Platform: Xilinx ISE 4.1, ModelSim , Visual C++ 6.0, Windows 2000 Professional

3 Pipelining It acts like an assembly line Ford’s Auto Assembly Line
Station 1 Station 2 Station 3 Station 4 Sequential Auto Production VS Pipelining Auto Production 1 2 3 4 Auto Production Time

4 Pipelined RISC In our Pipelined RISC Processor:
RISC is an acronym for Reduced Instruction Set Computer It has a reduced and simple instruction set It has a large number of general-purpose registers In our Pipelined RISC Processor: Each instruction takes 1 clock cycle for each stage The processor can accept 1 new instruction per clock Instructions are processed in stages as they pass down Multiple instructions in some phase of execution concurrently Pipelining doesn't improve the latency of instructions (each instruction still requires the same amount of time to complete) It does improve the overall throughput

5 Pipelined RISC Design

6 Instruction Fetch Stage

7 Instruction Decode Stage

8 Execution Stage

9 Memory Access Stage

10 Write Back Stage

11 Modified Pipelined RISC Design
16-bit ISA 16-bit fixed-length instructions, 16 registers no “funct” field for R-type, only “op” field limited number of operations 4-bit “opcode” field => maximum 16 operations 3 3 3 3 4 Suggested R-type opcode rs rt rd funct 4 4 4 4 R-type opcode rs rt rd 4 4 4 4 I-type opcode rs rt address 4 12 J-type opcode target address

12 Multiplier Algorithms
“Pencil-and-paper method” x requires M cycles for one NxM multiplication implemented with AND, adder, and shift register

13 Multiplier Algorithms
Array Multiplier

14 Multiplier Algorithms
Modified Booth Encoding (MBE) reduces number of partial products by N/2 for MxN multiplication performs parallel encoding v. serial encoding in original Booth

15 Multiplier Algorithms
Wallace Tree increases speed of summing by all bits of PP in each column are x-2 compressor composed of CSAs; P0j P1j P2j P3j P4j P5j P6j P7j P8j increased parallelism 3-2 compressor 3-2 compressor 3-2 compressor added independently and simultaneously c3j c2j c1j c3j-1 c2j-1 c1j-1 x := the number of PP’s in column 3-2 compressor 3-2 compressor c5j c4j c5j-1 c4j-1 4-2 compressor c6j c6j-1 Carry[j] Sum[j] 9-2 Compressor

16 Multiplier Design Issues and Solutions limited opcode size
made NOP instruction ADD $0, $0, $0 => freed one opcode ADD instruction doesn’t change register $0 (constant zero value) latency v. simplicity multiplier lies in critical path; must calculate product in one cycle algorithms trade simplicity of control and/or wiring for faster speed multiplier latency not detrimental if n is small enough => 8x8 multiplier negative and positive integer multiplication 8 LSB of 16-bit operand taken as a two’s complement number sign detection unit detects signs operands and sets product sign

17 Exception Managing Hardware
Pipeline Modifications EPC register tracks the problematic instruction EPC_2 register to hold the instruction to return to, if allowed Expansion of control unit to detect overflow signal and handle exception

18 Arithmetic Overflow Handler
Software Support Assurance that MEM and WB stages of pipeline continue execution

19 Arithmetic Overflow Handler
Software Support Assurance that MEM and WB stages of pipeline continue execution Interruption of program

20 Arithmetic Overflow Handler
Software Support Assurance that MEM and WB stages of pipeline continue execution Interruption of program Request to involve the operating system

21 Arithmetic Overflow Handler
Software Support Assurance that MEM and WB stages of pipeline continue execution Interruption of program Request to involve the operating system Enhancement of ISA “MFCO” - move from coprocessor “JR” - jump to address stored in reserved register

22 Overflow Example Instruction stored at address 103: 32 + 65527= 65559
Note: 216 = 65536 216 < 65559

23 Conclusion 16-bit processor, enhanced with a multiplier and able to detect arithmetic overflow Harvard Architecture model for memory management 14 multipurpose, 2 reserved registers Advantages and disadvantages of designed 16-bit ISA

24 References Boerger, Egon. Architecture Design and Validation Methods. New York Springer, 2000. Carpinelli, John D. Computer Systems Organization and Architecture. Boston: Addison-Wesley, Cohen, Ben. VHDL Coding Styles and Methodologies. Boston: Kluwer Academic Publishers, Dahan, David. 17x17-Bit, High-Performance, Fully Synthesizable Multiplier. Technology Licensing Division DSP Group Inc. Ercegovac, Milos D., Thomas Lang, and Jaime H. Moreno. Introduction to Digital Systems. New York: John Wiley & Sons, Inc., 1999. Hennessy, John L. and David A. Patterson. Computer Organization and Design. 2nd ed. San Francisco: Morgan Kaufmann Publishers Inc., High Speed Parallel Multiplier For LEON Processor Algorithm. Lab #5: Implementation of a Multiplier. EE116L course, UCLA. Nahata, Sunny and Rohit Madampath. 8 by 8 bit High Speed Multiplier Design Using (4,2) Counters Smith, James E. The Microarchitecture of Superscalar Processors. New York: Madison, 1995. Stalling, William. Computer Organization and Architecture. 6th ed. Upper Saddle River: Prentice Hall, 2003. Sweetman, Dominic. See MIPS Run. San Francisco: Morgan Kaufmann Publishers Inc., 1999. Tamir, Yuval. Computer Systems Architecture Notes. UCLA. Yeh, Wen-Chang and Chein-Wei Jen. High-Speed Booth Encoded Parallel Multiplier Design. IEEE Transactions on Computers, Vol. 49, No. 7. July 2000.


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