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Low Power Techniques That Dont Work CDNLive! September 11 th, 2007 Sandeep Mirchandani, Broadcom Corporation Bambuda Leung, Cadence Design Systems, Inc.

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Presentation on theme: "Low Power Techniques That Dont Work CDNLive! September 11 th, 2007 Sandeep Mirchandani, Broadcom Corporation Bambuda Leung, Cadence Design Systems, Inc."— Presentation transcript:

1 Low Power Techniques That Dont Work CDNLive! September 11 th, 2007 Sandeep Mirchandani, Broadcom Corporation Bambuda Leung, Cadence Design Systems, Inc.

2 2 © 2007 Broadcom Corporation. All rights reserved. Acknowledgements Broadcom – Balaji Krishnamachary – Jennifer Hwang – Kiran Puttegowda – Li-Yuan Chen – Sherman Hsu Cadence – Ted Schroeder – Marc Edwards – Bassilios Petrakis – Mitch Hines – Masood Makkar – Michael Munsey – Rich Owen

3 3 © 2007 Broadcom Corporation. All rights reserved. whats wrong with many low power techniques? Power is reduced in places where it doesnt count Reduction in one type of power increases another Design schedule and resources are consumed by implementation Technique doesnt produce expected power reduction Technique causes yield loss or functional failure Application software never uses low power modes Change in design or use model invalidates early analysis

4 4 © 2007 Broadcom Corporation. All rights reserved. reducing tiny power component is useless (at best)! power estimation dependent on use model (activity factor, temp,...) easy to feed erroneous assumptions into sophisticated tools and produce garbage results 4 © 2007 Broadcom Corporation. All rights reserved. reducing tiny power component is useless (at best)!

5 5 © 2007 Broadcom Corporation. All rights reserved. reducing tiny power component is useless (at best)! power estimation dependent on use model (activity factor, temp,...) easy to feed erroneous assumptions into sophisticated tools and produce garbage results 5 © 2007 Broadcom Corporation. All rights reserved. reducing tiny power component is useless (at best)!

6 6 © 2007 Broadcom Corporation. All rights reserved. reducing tiny power component is useless (at best)! power estimation dependent on use model (activity factor, temp,...) easy to feed erroneous assumptions into sophisticated tools and produce garbage results 6 © 2007 Broadcom Corporation. All rights reserved. reducing tiny power component is useless (at best)!

7 7 © 2007 Broadcom Corporation. All rights reserved. leakage reduction techniques power reduction technique complexity (both implementation and verification) potential static power savings clockgatin g highVt threshold biasing Low Leakage Process (LLP instead of G) stdcell height optimization power gating stack forcing body biasing input vector control variation reduction Vdd/Vt optimizatio n increasing gate length datapath tiling custom clocktee leakage reduction techniques often cost dynamic power...

8 8 © 2007 Broadcom Corporation. All rights reserved. clockgating is almost always effective and easy to implement clockgating pros – easy to implement : good tool support – generally saves both area and power clockgating cons – timing may be harder to meet – clockgate enables may not be activated for long enough to get power savings – redundant levels of clockgating may further mess up clocktree structure – placement of gated registers may cause excessive clocktree buffering – DFT coverage may require lots of testclock muxing –... but who caresits easy to implement

9 9 © 2007 Broadcom Corporation. All rights reserved. complex methods like power gating present a greater risk of not working power gating can have huge impact on schedule, area, resources, timing... early power gating decisions could turn out to be sub-optimal: – power gating granularity fine grain coarse grain block level number of power domains – on-chip vs off-chip switches sleep transistor or switch sizing – power modes and domain-crossing signals handshaking between blocks in different power domains managing clock skew at different voltage corners bus structures – power modes and state transitions – on-off vs DVFS domains – table lookup vs adaptive voltage-frequency pairs – save/restore time requirements

10 10 © 2007 Broadcom Corporation. All rights reserved. complex methods like power gating present a greater risk of not working power gating can have huge impact on schedule, area, resources, timing... many extra states and sequences – power mode entry/exit control, – state retention, hidden states – reset and boot sequencing – DFT and power management interaction... –... power gating schemes can break the design in unexpected ways – inrush current – sneak leakage path – missing level shifter or clamp – timing penalty of domain-crossing signals –... power distribution could be a nightmare – level shifter placement and power hookup – IRDrop verification – buffering of domain1 signals in domain2 region –.. verification is more complex – need to communicate design intent to many different tools – more needs to be verified later in design cycle –..

11 11 © 2007 Broadcom Corporation. All rights reserved. power gating breaks existing tools and design process

12 12 © 2007 Broadcom Corporation. All rights reserved. implementing power gating requires two types of checks: 1. topological checks to catch problems like: – 1.2V cells fed by 2.5V power – 1'b1 being assigned to wrong power – buffering of always-on signals with variable Vdd – missing or redundant clamps – incorrect clamp enable connections (wrong driver, wrong polarity) 2. simulation checks to catch problems like: – power up-and-down sequence – output corruption – incorrect isolation – invalid state transitions – state retention IUS CLP

13 13 © 2007 Broadcom Corporation. All rights reserved. Adding Power Gating to a Design

14 14 © 2007 Broadcom Corporation. All rights reserved. Adding Power Gating to a Design

15 15 © 2007 Broadcom Corporation. All rights reserved. Creating Power Domains create_power_domain – name green... create_power_domain –name blue... create_power_domain – name red –default …

16 16 © 2007 Broadcom Corporation. All rights reserved. Adding Shutoff Capability create_power_domain.... –shutoff_condition create_power_domain … –shutoff_condition

17 17 © 2007 Broadcom Corporation. All rights reserved. Why Isolation is required X

18 18 © 2007 Broadcom Corporation. All rights reserved. Isolation in Source X

19 19 © 2007 Broadcom Corporation. All rights reserved. Problem: Destination Shutoff X Off-to-On Domain Crossing

20 20 © 2007 Broadcom Corporation. All rights reserved. Isolation at Top Level X PM Precedence Requirement: Red > Blue

21 21 © 2007 Broadcom Corporation. All rights reserved. Problem: Red Buffer in Isolation Datapath X PM Precedence Requirement: Red > Blue Unprotected Off-to- On Domain Crossing

22 22 © 2007 Broadcom Corporation. All rights reserved. CLP Low Power Topological Checks Demo

23 23 © 2007 Broadcom Corporation. All rights reserved. Isolation Order Problem PMOFF PMGB PMG PMB Isolation De- asserted during mode change

24 24 © 2007 Broadcom Corporation. All rights reserved.


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