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Robust Window-based Multi-node Technology- Independent Logic Minimization Jeff L.Cobb Kanupriya Gulati Sunil P. Khatri Texas Instruments, Inc. Dept. of ECE, Texas A&M University 1

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Overview Introduction Background Previous work Approach Experimental results Conclusions 2

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Introduction VLSI design flow HDL (Verilog, VHDL) Logic optimization Physical design 3

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Introduction Purpose of logic optimization Reduce area Reduce power Reduce delay Logic optimization Technology-independent optimization Goal: reduce literal count Technology-dependent optimization 4

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Background Dont Cares Logic function allowed to have 0 or 1 as possible output for a given input ODCSDC XDC: External dont cares given 5

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Background Dont Cares Computed for one node at a time Cannot capture multi-node flexibility 6 xy (x+y) = xy(xy) + (x+y)(x+y) = xy+xy = x y Goal: multi-node logic minimization Yields a Boolean relation Need to determinize this relation for solution

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Background Boolean relations Can express more than one allowed output vector for a single input vector Dont cares only express flexibility for a single output 7

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Terminology 8

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Problem Definition 9 Implement dual-node Boolean relation- based multi-level logic minimization technique Goals: Method must scale to large designs Compare to best dont care-based method (single-node)

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Previous Work 10 [CM77] Formulated multi-node minimization problem No results provided [WW94] Multi-node minimization Extremely large runtimes, works on very small designs [MB05] Single node approach, uses windowing and SAT based formulation Used for comparison purposes This work: Efficient choice of nodes, window based, efficient quantification scheduling

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Approach Key features Dual node optimization Careful node pair selection Window based optimization technique Early quantification for efficiency 11

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Approach 12

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Node Pair Selection 13

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Node Pair Selection 14

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Node Pair Selection 15

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Node Pair Selection Compute common input ratio Compute common output ratio Select node pairs that satisfy 16

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Subnetwork Extraction 17

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Subnetwork Extraction 18

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Building the Relation where 19

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Quantification Scheduling 20

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Quantification Scheduling 21

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Quantification Scheduling 22

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Call BREL (a Boolean relation minimizer) to minimize Returns new nodes and Graft new nodes into Delete original nodes, Endgame 23

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BREL 24 BREL is a heuristic Boolean relation solver Solving a Boolean relation Same as minimum cost determinization of the relation (i.e. finding the lowest cost function which is contained in the relation) Branch and bound approach

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Experimental Results Implemented in SIS Uses CUDD ROBDD Package 15 benchmark circuits from mcnc91, itc99 Metric for quality: literal count Preprocessing steps: Removes constant-valued nodes Removes nodes that do not fanout Merges functionally identical nodes 25

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Experimental Results Parameter selection 4 parameters to node selection algorithm Goal: Find golden values 26

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Experimental Results Parameter: 27

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Experimental Results Parameters: : Window size : Partners for 28

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Experimental Results 29

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Experimental Results Parameter: 30

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Experimental Results Golden parameter values: Can be modified to balance quality/runtime 31

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Experimental Results Compared versus 12% lit. improvement 38x runtime increase But runtimes are still within 3-4 min Low memory (#BDD nodes) High gain (number of node pairs which give an improvement) 32

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Experimental Results Run after 13% lit. improvement Both use 2x2 windows 33

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Experimental Results Limit subnetwork size τ 34

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Conclusions 12% less literals than best DC approach Runtimes under 4 minutes for largest network Low memory usage Further reduce literals by 13% after running best DC approach Future Work Consider 3+ nodes in relation SAT-based relation construction Alternative to BREL 35

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36 Thank you!

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37 SAT-Sweep

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38 BREL

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39 BREL

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