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CSE3601 CSE 360: Introduction to Computer Systems Course Notes Rick Parent Wayne Heym.

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1 CSE3601 CSE 360: Introduction to Computer Systems Course Notes Rick Parent Wayne Heym Copyright © by Rick Parent, Todd Whittaker, Bettina Bair, Pete Ware, Wayne Heym

2 CSE3602 Information Representation 1 u Positional Number Systems: position of character in string indicates a power of the base (radix). Common bases: 2, 8, 10, 16. (What base are we using to express the names of these bases?) –Base ten (decimal): digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 form the alphabet of the decimal system. E.g., = –Base eight (octal): digits 0, 1, 2, 3, 4, 5, 6, 7 form the alphabet. E.g., =

3 CSE3603 Information Representation 2 –Base 16 (hexadecimal): digits 0-9 and A-F. E.g., 13C 16 = –Base 2 (binary): digits (called bits) 0, 1 form the alphabet. E.g., = –In general, radix r representations use the first r chars in {0…9, A...Z} and have the form d n-1 d n-2 …d 1 d 0. Summing d n-1 r n-1 + d n-2 r n-2 + … + d 0 r 0 will convert to base 10. Why to base 10?

4 CSE3604 Information Representation 3 u Base Conversions –Convert to base 10 by multiplication of powers E.g., = ( ) 10 –Convert from base 10 by repeated division E.g., = ( ) 8 –Converting base x to base y: convert base x to base 10 then convert base 10 to base y

5 CSE3605 Information Representation 4 –Special case: converting among binary, octal, and hexadecimal is easier t Go through the binary representation, grouping in sets of 3 or 4. E.g., = = = = D9 16 E.g., C3B 16 = ( ) 8

6 CSE3606 Information Representation 5 u What is special about binary? –The basic component of a computer system is a transistor (transfer resistor): a two state device which switches between logical 1 and 0 (actually represented as voltages on the range 5V to 0V). –Octal and hexadecimal are bases in powers of 2, and are used as a shorthand way of writing binary. A hexadecimal digit represents 4 bits, half of a byte. 1 byte = 8 bits. A bit is a binary digit. –Get comfortable converting among decimal, binary, octal, hexadecimal. Converting from decimal to hexadecimal (or binary) is easier going through octal.

7 CSE3607 Information Representation 6 BinaryHexDecimalBinaryHexDecimal A B C D E F15

8 CSE3608 Information Representation 7 u Ranges of values –Q: Given k positions in base n, how many values can you represent? –A: n k values over the range (0…n k -1) 10 n=10, k=3: 10 3 =1000 range is (0…999) 10 n=2, k=8: 2 8 =256 range is (0…255) 10 n=16, k=4: 16 4 =65536 range is (0…65535) 10 –Q: How are negative numbers represented?

9 CSE3609 Information Representation 8 u Integer representation: –Value and representation are distinct. E.g., 12 may be represented as XII, C 16, 12 10, and Note: -12 may be represented as -C 16, , and –Simple and efficient use of hardware implies using a specific number of bits, e.g., a 32-bit string, in a binary encoding. Such an encoding is fixed width. –Four methods: (fixed-width) simple binary, signed magnitude, binary coded decimal, and 2s complement. –Simple binary: as seen before, all numbers are assumed to be positive, e.g., 8-bit representation of = and =

10 CSE36010 Information Representation 9 –Signed magnitude: simple binary with leading sign bit. 0 = positive, 1 = negative. E.g., 8-bit signed mag.: = = What ranges of numbers may be expressed in 8 bits? Largest: Smallest: Extend to 12 bits:

11 CSE36011 Information Representation 10 Problems: (1) Compare the signed magnitude numbers and (2) Must have subtraction hardware in addition to addition hardware. –Binary Coded Decimal (BCD): use a 4 bit pattern to express each digit of a base 10 number 0000 = = = = = = = = = = = = - E.g., 123 : : :

12 CSE36012 Information Representation 11 BCD Disadvantages: –Takes more memory. 32 bit simple binary can represent more than 4 billion discrete values. 32 bit BCD can hold a sign and 7 digits (or 8 digits for unsigned values) for a maximum of 110 million values, a 97% reduction. –More difficult to do arithmetic. Essentially, we must force the Base 2 computer to do Base 10 arithmetic. BCD Advantages: –Used in business machines and languages, i.e., in COBOL for precise decimal math. –Can have arrays of BCD numbers for essentially arbitrary precision arithmetic.

13 CSE36013 Information Representation 12 –Twos Complement t Used by most machines and languages to represent integers. Fixes the -0 in the signed magnitude, and simplifies machine hardware arithmetic. t Divides bit patterns into a positive half and a negative half (with zero considered positive); n bits creates a range of [-2 n-1 … 2 n-1 -1]. CODE Simple Signed s comp

14 CSE36014 Information Representation 13 –Representation in 2s complement; i.e., represent i in n-bit 2s complement, where -2 n-1 i +2 n-1 -1 t Nonnegative numbers: same as simple binary t Negative numbers: –Obtain the n-bit simple binary equivalent of | i | –Obtain its negation as follows: Invert the bits of that representation Add 1 to the result t Ex.: convert to 16-bit 2s complement t Ex.: extend the 12-bit 2s complement number to 16 bits.

15 CSE36015 Information Representation 14 u Binary Arithmetic –Addition and subtraction only for now –Rules: similar to standard addition and subtraction, but only working with 0 and 1. t = = 0 t = = 1 t = = 0 t = = 1 –Must be aware of possible overflow. Ex.: 8-bit signed magnitude = Ex.: 8-bit signed magnitude =

16 CSE36016 Information Representation 15 u 2s Complement binary arithmetic –Addition and subtraction are the same operation –Still must be aware of overflow. Ex.: 8 bit 2s complement: = Ex.: 8 bit 2s complement: = Ex.: 8 bit 2s complement: =

17 CSE36017 Information Representation 16 –2s Complement overflow t Opposite signs on operands cant overflow t If operand signs are same, but results sign is different, must have overflow t Can two positives sum to positive and still have overflow? Can two negatives?

18 CSE36018 Information Representation 17 u Characters and Strings –EBCDIC, Extended Binary Coded Decimal Interchange Code t Used by IBM in mainframes (360 architecture and descendants). t Earliest system –ASCII, American Standard Code for Information Interchange. t Most common system –Unicode, t New international standard t Variable length encoding scheme with either 8- or 16-bit minimum t a unique number for every character, no matter what the platform, no matter what the program, no matter what the language.

19 CSE36019 Information Representation 18 u ASCII –see table 1.7 on pg. 18. t In Unix, run man ascii. –7 bit code t Printable characters for human interactions t Control characters for non-human communication (computer- computer, computer-peripheral, etc.) –8-bit code: most significant bit may be set t Extended ASCII (IBM), includes graphical symbols and lines t ISO 8859, several international standards t Unicodes UTF-8, variable length code with 8-bit minimum

20 CSE36020 ASCII u Easy to decode –But takes up a predictable amount of space u Upper and lower case characters are 0x20 (32 10 ) apart u ASCII representation of 3 is not the same as the binary representation of 3. –To convert ASCII to binary (an integer), 3-0 = 3 u Line feed (LF) character – = 0x0a = –\n = 0xa

21 CSE36021 Information Representation 19 u String: definition is programming language dependent. –C, C++: strings are arrays of characters terminated by a null byte. u Decode: , , , , , , , , , , , , , –Or (in hex): u How many bytes is this? u Whats the use of the 00 byte at the end?

22 CSE36022 Information Representation 20 u Simple data compression –ASCII codes are fixed length. –Huffman codes are variable length and based on statistics of the data to be transmitted. t Assign the shortest encoding to the most common character. –In English, the letter e is the most common. –Either establish a Huffman code for an entire class of messages, –Or create a new Huffman code for each message, sending/storing both the coding scheme and the message. t a widely used and very effective technique for compressing data; savings of 20% to 90% are typical, depending on the characteristics of the file being compressed. (Cormen, p. 337)

23 CSE36023 ECL - Expected Code Length CharFixed len encoding FreqVar len encoding # bitsExpected # bits Avg len21.75

24 CSE36024 Information Representation 21 t Huffman Tree for a man a plan a canal panama –Examine data set and determine frequencies of letters (example ignores spaces, normally significant) –Create a forest of single node trees. Choose the two trees having the smallest total frequencies (the two smallest trees), and merge them together (lesser frequency as the left subtree, for definiteness, to make grading easier). Continue merging until only one tree remains.

25 CSE36025 Information Representation 22 Huffman Tree for "a man a plan a canal panama" 'a'.4762 'n'.1905 'c'.0476 'l' 'm'.0952 'p' u Reading a 1 calls for following the left branch. u Reading a 0 calls for following the right branch. u Decoding using the tree: To decode 0001, start at root and follow r_child, r_child, r_child, l_child, revealing encoded m.

26 CSE36026 Information Representation 23 t Comparison of Huffman and 3-bit code example –3-bit: = 63 bits –Huffman: = 46 bits –Savings of 17 bits, or 27% of original message

27 CSE36027 Parity: Simple error detection u Data transmission, aging media, static interference, dust on media, etc. demand the ability to detect errors. u Single bit errors detected by using parity checking. u Parity, here, is the the state of being odd or even.

28 CSE36028 Information Representation 24 –How to detect a 1-bit error: Ex.: send ASCII S : send , but receive ? t Add a 1-bit parity to make an odd or even number of bits per byte. t Parity bit is stripped by hardware after checking. Sender/receiver both agree to odd or even parity. t 2 flipped bits in the same encoding are not detected.

29 CSE36029 Information Representation 25 u Two meanings for Hamming distance. 2 nd is generalization of 1 st. 1 st is: distance between two encodings of the same length. 1.A count of the number of bits different in encoding 1 vs. encoding 2. E.g.,dist(1100, 1001) = dist(0101, 1101) = 2.Generalize to an entire code by taking the minimum over all distinct pairs (2 nd meaning). –The ASCII encoding scheme has a Hamming distance of 1. –A simple parity encoding scheme has a Hamming distance of 2. u Hamming distance serves as a measure of the robustness of error checking (as a measure of the redundancy of the encoding).

30 CSE36030 ISEM FAQ 1 u Editing, Assembling, Linking, and Loading –There are three components to the Instructional SPARC Emulator (ISEM) package that we use for this class: t the assembler, t the linker, and t the emulator/debugger.

31 CSE36031 ISEM FAQ 2 u Editing –There are a number of programs that you can use to create your source files. t Emacs is probably the most popular; t vi is also available, but its command syntax is difficult to learn and use; t using pine program, you can use the pico editor, which combines many features of Emacs into a simple menu-driven facility. –Start Emacs by xemacs sourcefile.s &, which creates the file called sourcefile.s. –Use the tutorial, accessed by typing "Ctrl-H Ctrl-H t". –For other editors, you are on your own.

32 CSE36032 Example Sparc Assembly Language Instructions % type ! Assembler directive: data starts here. A_m, B_m, and A_m:.word ? ! C_m are symbolic constants. Furthermore, each B_m :.word 0x30 ! is an address of a certain-sized chunk of memory. Here, C_m :.word 0 ! each chunk is four bytes (one word) long. When the ! program gets loaded, each of these chunks stores a ! number in 2s complement encoding, as follows: At ! address C_m, zero; at B_m, 48; at A_m, 0x3F = 077 = 63..text! Assembler directive, instructions start here start:! Label (symbolic constant) for this address set A_m, %r2! Put address A_m into register 2 ld [%r2], %r2! Use r2 as an indirect address for a load (read) set B_m, %r3! Put address B_m into register 3 ld [%r3], %r3! Read from B_m and replace r3 w/ value at addr B_m sub %r2, %r3, %r2! Subtract r3 from r2, save in r2 set C_m, %r4! Put address C_m into register 4 st %r2, [%r4]! Store (write) r2 to memory at address C_m terminate:! Label for address where ta 0 instruction stored ta 0! Stop the program beyond_end:! Label for address beyond the end of this program

33 CSE36033 ISEM FAQ 3 u Assembling –The assembler is called "isem-as", and is the GNU Assembler (GAS), configured to cross-assemble to a SPARC object format. –It is used to take your source code, and produce object code that may be linked and run on the ISEM emulator. –The syntax for invoking the assembler is: isem-as [-a[ls]] sourcefile.s -o objectfile.o –The input is read from sourcefile.s, and the output is written to objectfile.o. –The option "-a" tells the assembler to produce a listing file. The sub-options "l" and "s" tell the assembler to include the assembly source in the listing file and produce a symbol table, respectively.

34 CSE36034 ISEM FAQ 4 u The listing file –Will identify all the syntactic errors in your program, and it will warn you if it identifies "suspicious" behavior in your source file. –Column 1 identifies a line number in your source file. –Column 2 is an offset for where this instruction or data resides in memory. –Column 3 is the image of what is put in memory, either the machine instructions or the representation of the data. –The final column is the source code that produced the line. –At the bottom of the file you will find the symbol table. –Again, the symbols are represented as offsets that are relocated when the program is loaded into memory.

35 CSE36035 isem-as -als labn.s -o labn.o >! labn.lst F A_m:.word ? B_m:.word 0x C_m:.word c text 6 start: set A_m, %r A C ld [%r2], %r c set B_m, %r E C600C000 ld [%r3], %r sub %r2, %r3, %r c set C_m, %r C st %r2, [%r4] 14 terminate: D02000 ta c beyond_end: DEFINED SYMBOLS A_m B_m C_m xmp0.s:6.text: start xmp0.s:14.text: terminate xmp0.s:16.text: c beyond_end NO UNDEFINED SYMBOLS Line in source file (.s) Offset to address in memory Contents at address in memory Labels are symbolic offsets

36 CSE36036 ISEM FAQ 5 u Linking –Linking turns a set of raw object file(s) into an executable program. –From the manual page, "ld combines a number of object and archive files, relocates their data and ties up symbol references. Often the last step in building a new compiled program to run is a call to ld." –Several object files are combined into one executable using ld; the separate files could reference symbols from one another. –The output of the linker is an executable program. –The syntax for the linker is as follows: isem-ld objectfile.o [-o execfile] Examples % isem-ld foo.o -o foo Links foo.o into the executable foo. % isem-ld foo.o Links foo.o into the executable a.out.

37 CSE36037 ISEM FAQ 6 u Loading/Running –Execute the program and test it in the emulation environment. –The program "isem" is used to do this, and the majority of its features are covered in your lab manual. –Invoke isem as follows isem [execfile] Examples % isem foo Invokes the emulator, loads the program foo % isem Invokes the emulator, no program is loaded –Once you are in the emulator, you can run your program by typing "run" at the prompt.

38 CSE36038 ISEM Debugging Tools 1 % isem xmp0 Instructional SPARC Emulator Copyright Computer Science Department University of New Mexico ISEM comes with ABSOLUTELY NO WARRANTY ISEM Ver 1.00d : Mon Jul 27 16:29:45 EDT 1998 Loading File: xmp bytes loaded into Text region at address 8: bytes loaded into Data region at address a:4000 PC: 08: nPC: PSR: e N:0 Z:0 V:0 C:0 start : sethi 0x10, %g2 ISEM> run Program exited normally. Assembly language programs are not notoriously chatty.

39 CSE36039 ISEM Debugging Tools 2 u reg –Gives values of all 32 general registers –Also PC u symb –Shows the resolved values of all symbolic constants u dump [addr] –Either symbol or hex address –Gives the values stored in memory ISEM> reg G f O L I PC: 08: c nPC: PSR: e N:0 Z:0 V:0 C:0 beyond_end : sethi 0x0, %g0 ISEM> symb Symbol List A_m : B_m : terminate : ISEM> dump A_m 0a: f f ? a: a:

40 CSE36040 ISEM Debugging Tools 3 u break [addr] –Set breakpoints in execution –Once execution is stopped, you can look at the contents of registers and memory. u trace –Causes one (or more) instruction(s) to be executed –Registers are displayed –Handy for sneaking up on an error when youre not sure where it is. u For the all-time most wanted list of errors (and their fixes) –

41 CSE36041 Basic Components 1 u Terminology from Ch. 2: –Flip flop: basic storage device that holds 1 bit –D flip flop: special flip flop that outputs the last value that was input to it (a data signal). –Clock: two different meanings: (1) a control signal that oscillates (low to high voltage) every x nanoseconds; (2) the write select line for a flip flop.

42 CSE36042 Basic Components 2 –Register: collection of flip flops with parallel load. Clock (or write select) signal controlled. Stores instructions, addresses, operands, etc. –Bus: Collection of related data lines (wires).

43 CSE36043 Basic Components 3 –Combinational circuits: implement Boolean functions. No feedback in the circuit, output is strictly a function of input. t Gates: and, or, not, xor E.g., xy + z

44 CSE36044 Basic Components 4 –Gates can be used in combination to implement a simple (half) adder. t Addition creates a value, plus a carry-out. Z = X Y CO = X Y X Y Z CO

45 CSE36045 Basic Components 5 –Sequential Circuits: introduce feedback into the circuit. Outputs are functions of input and current state. –Multiplexers: combinational circuits that use n bits to select an output from 2 n input lines. D C Q

46 CSE36046 Basic Components 6 u Von Neumann Architecture –Can access either instructions or data from memory in each cycle. –One path to memory (von Neumann bottleneck) –Stored program system. No distinction between programs and data

47 CSE36047 Basic Components 7 Examples of Von Neumann architecture to be explored in this course: u SAM: tiny, good for learning architecture u MIPS: texts example assembly language u SPARC: labs u M68HC11: used in ECE 567 (taken by CSE majors) Roughly, the order of presentation in this course is as follows: u A couple of days on the Main Memory System u Weeks on the Central Processing Unit (CPU) u Finish the course with the I/O System

48 CSE36048 Basic Components 8 u Memory: Can be viewed as an array of storage elements. –The index of each element is called the address. –Each element holds the same number of bits. How many bits per element? 8, 16, 32, 64? n n n n-1 8 bits = 1 byte16 bits32 bits64 bits

49 CSE36049 Memory Element & Address Sizes If a machines memory is 5-bit addressable, then, at each distinct address, 5 bits are stored. The contents at each address are represented by 5 bits. If 3 bits are used to represent memory addresses, then the memory can have at most 2 3 = 8 distinct addresses. Such a memory can store at most 8 5 = 40 bits of data. If the data bus is 10 bits wide, then up to 10 bits at a time can be transferred between memory and processor; this is a 10-bit word. Address Contents DecimalBinary

50 CSE36050 Basic Components 9 u Lets look deeper. –Suppose each memory element is stored in a bank and given a relative address. –You could have several such banks in your memory. –The GLOBAL address of each element would be: [relative address] & [bank address]. –To get two elements at a time, start reading from bank 0 (dont start from bank 1; this would be a memory address not aligned error) Bank Bank Bank Global addresses, not contents. Think of the contents as being underneath the global addresses.

51 CSE36051 Basic Components 10 –Memory alignment: Assume a byte addressable machine with 4-byte words. Where are operands of various sizes positioned? t bytes: on a byte boundary (any address) t half words: on half word boundary (even addresses) t words: on word boundary (addresses divisible by 4) t double words: on double word boundary (addresses divisible by 8)

52 CSE36052 Contrast with bit ordering Basic Components 11 u Byte ordering: how numeric data is stored in memory –Ex.: = 0EC699BF 16 –Stored at address 0 0OE 1C BF C6 30E Big Endian High order (big end) is at byte Little Endian Low order (little end) is at byte 0

53 CSE36053 Basic Components 12 u Read/Write operations: must know the address to read or write. (read = fetch = load, write = store) t CPU puts address on address bus t CPU sends read signal –(R/ W=1, CS=1) –(Read/dont Write, Chip Select) t Wait t Memory puts data on data bus –reset (CS=0) D0 D1 D(n-1) A0 A1 A(m-1) CS R/ W

54 CSE36054 Basic Components 13 –Types of memory: t ROM: Read Only Memory: non-volatile (doesnt get erased when powered down; its a combinational circuit!) t PROM: Programmable ROM: use a ROM burner to write data to it initially. Cant be re-written. t EPROM: Erasable PROM. Uses UV light to erase. t EEPROM: Electrically Erasable PROM. t RAM: Random access memory. Can efficiently read/write any location (unlike sequential access memory). Used for main memory. –Many variations (types) of RAM, all volatile SDRAM, DDR SDRAM RDRAM

55 CSE36055 Basic Components 14 u CPU: executes instructions -- primitive operations that the computer can perform. –E.g.,arithmeticA+B data movementA := B controlif expr goto label logicalAND, OR, XOR… t Instructions specify both the operation and the operands. An encoded operand is often a location in memory where the value of interest may be found (address of value of interest).

56 CSE36056 Basic Components 15 –Instruction set: all instructions for a machine. Instruction format specifies number and type of operands. t Ex.: Could have an instruction like ADD A, B, R Where A, B, and R are the addresses of operands in memory. The result is R := A+B.

57 CSE36057 Basic Components 16 –Actually, the instruction might be represented in a source file as: 0x C20422C20520A. … A D D A, B, R As such, it is an assembly language instruction. –An assembler might translate it to, say, 0x504C, the machines representation of the instruction. As such, it is a machine language instruction.

58 CSE36058 A Simple Instruction Set 1 u Simple instruction set: the Accumulator machine. –Simplify instruction set by only allowing one operand. Accumulator implied to be the second operand. –Accumulator is a special register. Similar to a simple calculator. ADD addrACC ACC + M[addr] SUB addrACC ACC - M[addr] MPY addrACC ACC * M[addr] DIV addrACC ACC / M[addr] LOAD addrACC M[addr] STORE addrM[addr] ACC

59 CSE36059 A Simple Instruction Set 2 Ex.: C = A B + C D LOAD 20! 1)Acc<-M[20] MPY 21! 2)Acc<-Acc*M[21] STORE 30! M[30]<-Acc LOAD 22! 3)Acc<-M[22] MPY 23! 4)Acc<-Acc*M[23] ADD 30! 5)Acc<-Acc+M[30] STORE 22! M[22]<-Acc –Machine language: Converting from assembly language to machine language is called assembling. Accumulator 1) 2) 3) 4) 5)

60 CSE36060 An Instruction (Encoding) Format t Assume 8-bit architecture. Each instruction may be 8 bits. 3 bits hold the op-code and 5 bits hold the operand. t How much memory can we address? t How many op-codes can we have? t Convert the mnemonic op-codes into binary codes.

61 CSE36061 A Simple Instruction Set 4 t Hand assemble our program: LOAD MPY STORE t Instructions are stored in consecutive memory:

62 CSE36062 A Simple Instruction Set 5

63 CSE36063 A Simple Instruction Set 6 –Control signals: control functional units to determine order of operations, access to bus, loading of registers, etc.

64 CSE36064 CPU

65 CSE36065 A Simple Instruction Set State Y N 4 5 Y N 7 8 6

66 CSE36066 State 0: Control Signals 2, 5, 9, 3 Put the address of the next instruction in the Addr Register and Inc. PC.

67 CSE36067 State 1: Control Signals 13, 14 Fetch the word of memory at Address, and load into Data Register.

68 CSE36068 State 2: Control Signals 6, 4 Send the word from the Data Register to the Instruction Register.

69 CSE36069 State 3: Control Signals 12, 5 Put the address from the instruction in the Address Register.

70 CSE36070 After State 3, what values are now stored in each register? u PC u MAR u MDR u IR u ACC

71 CSE36071 State 4: Control Signals 0, 7 Take the value from the ACCumulator and store it in the Data Register.

72 CSE36072 State 5: Control Signal 13 Write the data from the Data Register to the address stored in the MAR.

73 CSE36073 State 6: Control Signals 13, 14 Load the word at the Address from the Addr Reg into the Data Register.

74 CSE36074 After State 6, what values are now stored in each register? u PC u MAR u MDR u IR u ACC

75 CSE36075 State 7: Control Signals 6, 1 Load the word from Data Register into the ACCumulator.

76 CSE36076 State 8: Control Signals 6, 8, 10/11, 1 Use word from the Data Register for Arith Op and put result in ACC.

77 CSE36077 New Instruction What is necessary to implement a new instruction? New states? New control signals? New fetch/execute cycle? An Example: SWAP Exchange value in Accumulator with value at Address SWAP addr ! Acc <- #M[addr], M[addr] <- #Acc

78 CSE36078 New Instruction u What changes to fetch/execute cycle? –The fetch part of the cycle usually remains the same. –Recall the values stored in registers after each state t E.g., After State 6, t what values are in each register? –PC –MAR –MDR –IR –ACC t Handy to have #M[addr] in MDR –Start after state 6 then….

79 CSE36079 New State 9: Control Signals 6, 5 Save the Data value from the MDR in the Address Register. MDR -> bus Load MAR

80 CSE36080 New State 10: Control Signals 0, 7 Send the ACCumulator value to the Data Register. ACC -> bus load MDR

81 CSE36081 New State 11: Control Signals ?, 1 Put the saved value from the MAR into the ACCumulator. MAR->bus load ACC Note: there is no control signal in the current architecture opposite of 5 (Load MAR), so we would have to create a new control signal (MAR to bus) in addition to creating these new states.

82 CSE36082 New State 12 (Old 3): Control Signals 12, 5 Put (reload) the address from the instruction in the Address Register. Addr -> bus load MAR

83 CSE36083 New State 13 (Old 5): Control Signals 13 Write the data from the Data Register to the address stored in the MAR. CS

84 CSE36084 New Instruction Example Summary u Changes to States, added 9 thru 13 u Changes to Signals, added 15: MAR -> bus u Changes to Fetch/Execute, new register transfer language (RTL) PC -> bus, load MAR, INC -> PC, Load PC CS, R/w MDR -> bus, load IR Addr -> bus, load MAR CS, R/w MDR -> bus, load MAR ACC -> bus, load MDR MAR -> bus, load ACC Addr -> bus, load MAR CS

85 CSE36085 Instruction Set Architectures 1 u RISC vs. CISC –Complex Instruction Set Computer (CISC): many, powerful instructions. Grew out of the need for high code density. Instructions have varying lengths, number of operands, formats, and clock cycles in execution. –Reduced Instruction Set Computer (RISC): fewer, less powerful, optimized instructions. Grew out of opportunity for simpler, faster hardware. Instructions have fixed length, number of operands, formats, and similar number of clock cycles in execution.

86 CSE36086 Instruction Set Architectures 2 u Motivation: memory is comparatively slow. –10x to 20x slower than processor. –Need to minimize number of trips to memory. t Provide faster storage in the processor -- registers. t Registers (16, 32, 64 bits wide) are used for intermediate storage for calculations, or repeated operands. t Accumulator machine –One data register -- ACC. –2 memory accesses per instruction -- one for the instruction and one for the operand. t Add more registers (R0, R1, R2, …, Rn)

87 CSE36087 Instruction Set Architectures 3 u How many addresses to specify? –With binary operations, need to know two source operands, a destination, and the operation. E.g., op (dest_operand) (src_op1) (src_op2) –Based on number of operands, could have: t 3 addr. machine: both sources and dest are named. t 2 addr. machine: both sources named, dest is a source. t 1 addr. machine: one source named, other source and dest. is the accumulator. t 0 addr. machine: all operands implicit and available on the stack.

88 CSE36088 Instruction Set Architectures 4 1-address architecture: a:=a b+c d e –Memory onlyUsing registers t 1½-address architecture: at least one operand must always be a register. (½ address is register, 1 address is the memory operand: LOAD 100, R1). –Like an accumulator machine, but with many accumulators.

89 CSE36089 Instruction Set Architectures 5 3-address architecture: a:=a b+c d e –Using memory only: –Using registers: –What about instruction size?

90 CSE36090 Instruction Set Architectures 6 2-address architecture: a:=a b+c d e –Using memory only: –Using registers: –Most CISC arch. this way, making 1 operand implicit

91 CSE36091 Instruction Set Architectures 7 0-address architecture: a:=a b+c d e –Stack machine: All operands are implicit. Only push and pop touch memory. All other operands are pulled from the top of stack, and result is pushed on top. E.g., HP calculators.

92 CSE36092 Instruction Set Architectures 8 u Load/Store Architectures -- RISC –Use of registers is simple and efficient. Therefore, the only instructions that can access memory are load and store. All others reference registers.

93 CSE36093 Instruction Set Architectures 9 u Why load/store architectures? –Number of instructions (hence, memory references to fetch them) is high, but can work without waiting on memory. –Claim: overall execution time is lower. Why? t Clock cycle time is lower (no micro code interpretation). t More room in CPU for registers and memory cache. t Easier to overlap instruction execution through pipelining. –Side effects: t Register interlock: delaying execution until memory read completes. t Instruction scheduling: rearranging instructions to prevent register interlock (loads on SPARC) and to avoid wasting the results of pipelined execution (branches on SPARC).

94 CSE36094 SPARC Assembly Language 1 u SPARC (Scalable Processor ARChitecture) –Used in Sun workstations, descended from RISC-II developed at UC Berkeley –General Characteristics: t 32-bit word size (integer, address, register size, etc.) t Byte-addressable memory t RISC load/store architecture, 32-bit instruction, few addressing modes t Many registers (32 general purpose, 32 floating point, various special purpose registers) –ISEM: Instructional SPARC Emulator - nicer than a real machine for learning to write assembly language programs.

95 CSE36095 SPARC Assembly Language 2 u Structure –Line oriented: 4 types of lines t Blank - Ignored t Labeled - –Any line may be labeled. Creates a symbol in listing. Labels must begin with a letter (other than L), then any alphanumeric characters. Label must end with a colon :. Label just assigns a name to an address. Assembler Directives - E.g.,.data.word.text, etc. t Instructions –Comments start after ! character and go to the end of the x_m:.word 0x42 y_m:.word 0x20 z_m:.word 0.text start: set x_m, %r2 ld [%r2], %r2 set y_m, %r3 ld [%r3], %r3 ! Load x into reg 2 ! Load y into reg 3

96 CSE36096 SPARC Assembly Language 3 u Directives: Instructions to the assembler –Not executed by the -- following section contains declarations –Each declaration reserves and initializes a certain number of bits of storage for each of zero or more operands in the declaration..word bits.half bits.byte -- 8 bits E.g.,.data w:.half x:.byte 8 y:.byte m, 0x6e, 0x0, 0, 0 z:.word 0x3C5F.text -- following section contains executable instructions

97 CSE36097 SPARC Assembly Language 4 u Registers bits wide –32 general purpose integer registers, known by several names to the assembler %r0-%r7 also known as %g0-%g7 global registers -- Note, %r0 always contains value 0. %r8-%r15 also known as %o0-%o7 output registers %r16-%r23 also known as %l0-%l7 local registers %r24-%r31 also known as %i0-%i7 input registers t Use the %r0-%r31 names for now. Other names are used in procedure calls. –32 floating point registers %f0-%f31. Each reg. is single precision. Double prec. uses reg. pairs.

98 CSE36098 SPARC Assembly Language 5 u Assembly language –3-address operations - format different from book op src1, src2, dest !opposite of text E.g., add %r1, %r2, %r3 !%r3 %r1 + %r2 or %r2, 0x0004, %r2 !%r2 %r2 b-w-or 0x0004 –Contrast SPARC with MiPs (used in the book) t indirect address vs [addr] t operand order, especially the destination register t register notation: R2 vs. %r2 t branches

99 CSE36099 SPARC Assembly Language 6 –2-address operations: load and store ld [addr], %r2 ! %r2 M[addr] st %r2, [addr] ! M[addr] %r2 Often use set to put an address (a label, a symbolic constant) into a register, followed by ld to load the data itself. set x_m, %r1 !put addr x_m into %r1 ld [%r1],%r2 !use addr in %r1 to load %r2 –Immediate values: instruction itself contains some data to be used in execution.

100 CSE SPARC Assembly Language 7 –Immediate values (continued) E.g., add %rs, siconst 13, %rd !%rd %rs+const t Constant is coded into instruction itself, therefore available after fetching the instruction (no extra trip to memory for an operand). t On SPARC, no special notation for differentiating constants from addresses because no ambiguity in a load/store architecture. t Immediate value coded in 13 bit sign-extended value. Range is, then, … or to t Immediate values can be specified in decimal, hexadecimal, octal, or binary. E.g., add %r2, 0x1A, %r2 ! %r2 %r2 + 26

101 CSE SPARC Assembly Language 8 –Synthetic Instructions: assembler translates one instruction into several machine instructions. set : used to load a 32-bit signed integer constant into a register. Has 2 operands - 32 bit value and register number. How does that fit into a 32 bit instruction? E.g., set iconst 32, %rd set -10, %r3 set x_m, %r4 set =, %r8 clr %rd : used to set all bits in a register to 0. How? mov %rs, %rd : copies a register. neg %rs, %rd : copies the negation of a register.

102 CSE SPARC Assembly Language 9 –Operand sizes t double word = 8 bytes, word = 4 bytes, half word = 2 bytes, byte = 8 bits. Recall memory alignment issues. set x_m, %r2 !Put addr x_m in %r2 ld [%r2], %r1 !load word ldsb [%r2], %r1 !load byte, sign extended ldub [%r2], %r1 !load byte, extend with 0s st %r1, [%r2] !store word, addr is mult of 4 stb %r1, [%r2] !store byte, any address sth %r1, [%r2] !store half word, address is even – Characters use 8 bits t ldub to load a character t stb to store a character

103 CSE SPARC Assembly Language 10 –Traps : provides initial help with I/O, also used in operating systems programming. ta 0 : terminate program ta 1 : output ASCII character from %r8 ta 2 input ASCII character into %r8 ta 4 : output integer from %r8 in unsigned hexadecimal ta 5 : input integer into %r8, can be decimal, octal, or hex E.g., set =, %r8 !put = in %r8 ta 1 !output the = ta 5 !read in value into %r8 mov %r8, %r1 !copy %r8 into %r1 set 0x0a, %r8 !load a newline into %r8 ta 1 !output the newline

104 CSE SPARC Assembly Language 11 –More assembler directives (.asciz and.ascii): t Each of the following two directives is equivalent: –msg01:.asciz "a phrase" –msg01:.byte 'a', ' ', 'p', 'h', 'r'.byte 'a', 's', 'e', 0 t Note that.asciz generates one byte for each character between the quote (") marks in the operand, plus a null byte at the end. t The.ascii directive does not generate that extra byte. Each of the following three directives is equivalent: –digits:.ascii " " –digits:.byte '0', '1', '2', '3', '4', '5'.byte '6', '7', '8', '9' –digits:.byte 0x30, 0x31, 0x32, 0x33, 0x34.byte 0x35, 0x36, 0x37, 0x38, 0x39

105 CSE SPARC Assembly Language 12 –Quick review of instructions so far: ld [addr], %rd! %rd M[addr] st %rd, [addr]! M[addr] %r2 t op %rs1, %rs2, %rd! op is ALU op op %rs, siconst 13, %rd! %rd %rs op const set siconst 32, %rd! %rd const t ta #! trap signal –Have actually seen many more variants, e.g., ldub, ldsb, sth, clr, mov, neg, add, sub, smul, sdiv, umul, udiv, etc. Can evaluate just about any simple arithmetic expression.

106 CSE Review: Sparc Loads, x_m:.word 0xa1b2c3d4.skip 12.text set x_m, %r2 ld [%r2], %r3 ldsb [%r2], %r4 ldub [%r2], %r5 st %r3, [%r2+4] sth %r3, [%r2+8] stb %r3, [%r2+12] ta 0 After this runs, what values are in %r2-5, and memory locations starting at byte address x_m?

107 CSE Flow of Control 1 u In addition to sequential execution, need ability to repeatedly and conditionally execute program fragments. –High level language has: while, for, do, repeat, case, if-then-else, etc. –Assembler has if, goto. –Compare: high level vs. pseudo-assembler, implementation of f=n! f = 1 i = 2 loop: if (i > n) goto done f = f * i i = i + 1 goto loop done:... f = 1; i = 2; while (i <= n) { f = f * i; i = i + 1; }

108 CSE Flow of Control 2 –Branch -- put a new address in the program counter. Next instruction comes from the new address, effectively, a goto. –Unconditional branch (book) BRANCH addr ! PC addr (SPARC) ba addr ! PC addr –Conditional branch (book) BRcc R1, R2, target if R1 cc R2 then PC target and cc is comparison operation (e.g., LT is, GE is, etc.)

109 CSE Flow of Control 3 –Evaluating conditional branches t Evaluate condition If condition is true, then PC target, else PC PC+1 –Consider changes to the fetch-execute cycle given earlier for accumulator machine. What needs to change?

110 CSE Flow of Control 4 t Other conditions (from text, very similar to MIPS) Can implement high level control structures now. Back to the factorial example using the books assembly language: LOADR1,#1; R1 = f = 1 LOADR2,#2; R2 = i = 2 LOADR3, n; R3 = n loop:BRGTR2,R3,done; branch if i > n MPYR1,R1,R2; f = f * i ADDR2,R2,#1; i = i + 1 BRANCHloop; goto loop done:STOREf,R1; f = n!

111 CSE Flow of Control 5 –Condition Codes t Books assembly language has 3-address branches. SPARC uses 1-address branches. Must use condition codes. t Non-MIPS machines use condition codes to evaluate branches. Condition Code Register (CCR) holds these bits. SPARC has 4-bit CCR. N: Negative, Z: Zero, V: Overflow, C: Carry. All are shown in a trace, or in the reg command under ISEM. Condition codes are not changed by normal ALU instructions. Must use special instructions ending with cc, e.g., addcc.

112 CSE Flow of Control 6.text start: set 1, %r2 set 0xFFFFFFFE, %r1! –2 in 32-bit 2s comp cc_set: subcc %r1, %r2, %r3! r3<= -2-1 end: ta 0 ISEM> reg G fffffffe O L I PC: 08: nPC: c PSR: e N:0 Z:0 V:0 C:0 cc_set : subcc %g1, %g2, %g3 ISEM> trace G fffffffe fffffffd O L I PC: 08: c nPC: PSR: 00b0003e N:1 Z:0 V:0 C:0

113 CSE Flow of Control 7 –Setting the condition codes t Regular ALU operations dont set condition codes. Use addcc, subcc, smulcc, sdivcc, etc., to set condition codes. E.g., Suppose %r1 contains -4 and %r2 contains 5. addcc %r1, %r2, %r3 subcc %r1, %r2, %r3 subcc %r2, %r1, %r3 subcc %r1, %r1, %r3

114 CSE ALU Hardware 1 u How does a computer add? –Design a circuit that adds three single digit binary numbers. Results in a sum, and a carry out. xy c out c in Sum FA xy c out c in Sum

115 CSE ALU Hardware 2 u Now cascade the full adder hardware u How are CCR bits set? (Above is a ripple-carry adder.) –C-bit = C out –V-bit = C out C n-1 –Z-bit = (rz n-1 rz n-2 rz n-3... rz 0 ) –N-bit = rz n-1 FA 0 register xregister y register z FA c out FA

116 CSE Flow of Control 8 –Branches use logic to evaluate CCR (SPARC) OperationAssembler SyntaxBranch Condition Branch always batarget 1 (always) Branch never bntarget 0 (never) Branch not equal bnetarget Z Branch equal betarget Z Branch greater bgtarget (Z (N V)) Branch less or equal bletarget (Z (N V)) Branch greater or equal bgetarget (N V) Branch less bltarget N V Branch greater, unsigned bgutarget (C Z) Branch less or equal, unsigned bleutarget C Z Branch carry clear bcctarget C Branch carry set bcstarget C Branch positive bpostarget N Branch negative bnegtarget N Branch overflow clear bvctarget V Branch overflow set bvstarget V

117 CSE Flow of Control 9 –Setting Condition Codes (continued) Synthetic instruction cmp %rs1, %rs2 –Sets CCR, but doesn't modify any registers. –Implemented as subcc %rs1, %rs2, %g0 t Back to the factorial example (SPARC) set 1, %r1! %r1 = f = 1 set 2, %r2! %r2 = i = 2 set n, %r3! Get loc of n ld [%r3], %r3! Put n in %r3 loop:cmp %r2, %r3! Set CCR (i?n) bg done! i > n done nop! Branch delay umul %r1, %r2, %r1! f = f * i add %r2, 1, %r2! i = i + 1 ba loop! Goto loop nop! Branch delay done:set f, %r3! Get loc of f st %r1, [%r3]! f = n!

118 CSE Flow of Control 10 –Branch delay slots: unique to RISC architecture t Non-technical explanation: processor is running so fast, it cant make a quick turn. –Instruction following branch is always executed. t Technical explanation: the efficiency advantage of pipelining is greater if the following instruction, which has almost completed execution, is allowed to complete. t Compilers take advantage of branch delay slots by putting a useful instruction there if possible. For our purposes, use the nop (no operation) instruction to fill branch delay slots. Beware! Forgetting the nop will be a large source of errors in your programs!

119 CSE High Level Control Structures 1 u Converting high level control structures –You get to be the compiler. t Some compilers convert the source language (C, Pascal, Modula 2, etc.) into assembly language and then assemble the result to an object file. GNU C, C++ do this to GAS (Gnu Assembler). –if-then-else, while-do, repeat-until are all possible to create in a structured way in assembly language.

120 CSE High Level Control Structures 2 u General guidelines –Break down into independent (or nested) logical units –Convert to if/goto pseudo-code. –Mechanical, step-by-step, non-creative process f=1 i=2 loop: if (i>n) goto done f = f*i i = i+1 goto loop done:... f = 1; for (i=2; i<=n; i++) f = f * i;

121 CSE High Level Control Structures 3 t if-then-else if (a= b) goto else c = d + 1 goto end else: c = 7 end: init: set a, %r2 ! get &a into r2 ld [%r2], %r2 ! get a into r2 set b, %r3 ! get &b into r3 ld [%r3], %r3 ! get b into r3 if: cmp %r2, %r3 ! a ?? b (want >=) bge else ! a >= b, do then nop set d, %r5 ! get &d into r5 ld [%r5], %r5 ! get d into r5 add %r5, 1, %r4 ! r4 <- d+1 ba end nop else: set 7, %r4 ! get 7 into r4 end: set c, %r5 ! get &c into r5 st %r4, [%r5] ! c <- r4

122 CSE High Level Control Structures 4 u while loops: while (a=b) goto done body:a = a+1 goto whle done:c = d init: set a, %r4 ! get &a into r4 ld [%r4], %r2 ! get a into r2 set b, %r3 ! get &b into r3 ld [%r3], %r3 ! get b into r3 whle: cmp %r2, %r3 ! a ?? b (want >=) bge done ! a >= b skip body nop body: add %r2, 1, %r2 ! r2 = a + 1 st %r2, [%r4] ! a = a + 1 ba whle ! repeat loop body nop done: set c, %r5 ! get &c into r5...

123 CSE High Level Control Structures 5 t repeat-until loops: repeat … until (a>b) t if/goto: repeat: … if (a<=b) goto repeat nop

124 CSE High Level Control Structures 6 Complex condition if((a =c)) … if((a =c)) … u These can be combined and used in if/else or while loops.

125 CSE Flow of Control 11 –Optimizing code: change order of instructions, combine instructions, take advantage of branch delay slots. Factorial example again. ( for i:=n downto 1 do… ) t Reduced 7 instructions in loop to just 4. t (You gain no advantage if you optimize code in your labs.) set 1, %r1 ! %r1=f=1 set n, %r2! Get loc of n ld [%r2], %r2! Put n in %r2 loop:umul %r1, %r2, %r1! f=f*n subcc %r2, 1, %r2! Decrement n bg loop! Repeat nop! Branch delay set f, %r3! Get loc of f st %r1, [%r3]! f=n!

126 CSE Synthetic Instructions u Remember lab0?.data x_m:.word 0x42 y_m:.word 0x20 z_m:.word 0.text start: set x_m, %r2 ld [%r2], %r2 set y_m,%r3 ld [%r3], %r3 and so on… Suppose you gave this command to ISEM (after loading): ISEM> dump start start a0 00 c Could you find the set instruction?

127 CSE Instruction Encodings 1 u First, Instruction Encoding is how instructions are assembled –All instructions must fit into 32 bits. Register-register: op=10, i=0 Register-immediate: op=10, i=1 Floating point: op=10, i=0

128 CSE Instruction Encodings 2 Call instructions: op=01 Branch instructions: op=00, op2=010 SETHI instructions: op=00, op2=100 Ex.: add %r2, %r3, %r4 in hexadecimal: a

129 CSE Understanding SET Synthetic Usually used to put the value of an address in memory into a register. For example, set 0x4004, %r3 Can do neither add %r0, 0x4004, %r3 nor or %r0, 0x4004, %r3. Why not? SET is a synthetic instruction which may be implemented in two steps. #2 #1 Machine language encoding for 'set 0x4004, %r3'

130 CSE Decoding an Instruction Instruction Group (bits 30:31) = 00 Destination Register (bits 25:29) = Op Code (bits 22:24) = 100 Constant (bits 0:21) = Meaning: sethi 0x10, %r2 %r2 < (0x4000)

131 CSE More Decoding E0 04

132 CSE SET Synthetic Instruction u set iconst, rd sethi %hi(iconst), rd or rd, %lo(iconst), rd --or-- sethi %hi(iconst), rd --or-- or %g0, iconst, rd

133 CSE Bitwise Operations 1 u Bit Manipulation Instructions –Bitwise logical operations t and %rs1, %rs2, %rd … (32 bits) … t or %rs1, %rs2, %rd … (32 bits) … t xor %rs1, %rs2, %rd … (32 bits) …

134 CSE Bitwise Operations 2 t andn %rs1, %rs2, %rd … (32 bits) … orn %rs1, %rs2, %rd … (32 bits) … t not %rs, %rd … (32 bits) Recall the cc operations, so andcc, orcc, etc. are available. (However, there is no notcc ; use xnorcc.)

135 CSE Bitwise Operations 3 For what kinds of things are these bit level operations used? Recall the synthetic operation clr, and mov. clr %r2 or %r0, %r0, %r2 mov %r2, %r3 or %r0, %r2, %r3 t Masking operations: Want to select a bit or group of bits from a set of 32. E.g., convert lower (or upper) to upper case: a in binary is A in binary is All we need to do is turn off the bit in position 5. and %r1, 0b , %r1 will turn off that bit! t What if we subtract 32 (0b100000) from %r1? t What about converting upper to lower case?

136 CSE Bitwise Operations 4 –Bitwise shifting operations Shift logical left: sll %rs1, %rs2, %rd %rs1 : data to be shifted %rs2 : shift count %rd : destination register E.g., set 0xABCD1234, %r2 sll %r2, 3, %r3 %r2: %r3: t sll is equivalent to multiplying by a power of 2 (barring overflow). (In the decimal system, whats a shortcut for multiplying by a power of ten?)

137 CSE Bitwise Operations 5 Shift Logical Right: srl %rs1, %rs2, %rd –Shifts right instead of left, inserting zeros. Arithmetic shifts: propagate the sign bit when shifting right, e.g., sra. (Left shift doesn't change.) –Almost equivalent to dividing by a power of 2. t Rotating shifts: Bits that would have gone into the bit bucket are shifted in instead. (E.g., rr, rl) –Rotate not implemented in SPARC

138 CSE More SPARC Assembly Language Assembler directives t Are not encoded as machine instructions Memory alignment:.align 4 –Used when mixing allocations of bytes, words, halfwords, etc. and need word boundary alignment Reserve bytes of space:.skip 20 –Useful for allocating large amounts of space (e.g., arrays) Create a symbolic constant:.set mask, 0x0f –Can now use the word mask anywhere we could use the constant 0x0f previously All this is leading to additional addressing modes, which help us work with pointers, arrays, and records in assembly language.

139 CSE Addressing Modes 1 u Addressing Modes –How do we specify operand values? t In a register, location is encoded in the instruction. t As a constant, immediate value is in the instruction. t In memory, operand is somewhere in memory, location may only be known at runtime. –Memory operands: t Effective address: actual location of operand in memory. This may be calculated implicitly (e.g., by a displacement in the instruction) or may be calculated by the programmer in code.

140 CSE Addressing Modes 2 –Summary of addressing modes:

141 CSE Addressing Modes 3 –Memory Direct addressing t Entire address is in the instruction (not in SPARC). E.g., accumulator machine: each instruction had an opcode and a hard address in memory. –Cant be done on SPARC because an address is 32 bits, which is the length of an instruction. No room for opcodes, etc. Can be done in CISC because multi-word instructions are permitted. –Memory Indirect addressing t Pointer to operand is in memory. Instruction specifies location of pointer. Requires three memory fetches (one each for instruction, pointer, and data). Not in RISC machines because instruction is too slow; such an instruction would cause its own register interlock!

142 CSE Addressing Modes 4 –Register Indirect addressing t Register has address of operand (a pointer). Instruction specifies register number, effective address is contents of register. n_m:.word 5 ; initialize n to 5.text set n_m, %r1 ; %r1 has n_m, pointer to n ld [%r1], %r3 ; fetch n into %r3

143 CSE Addressing Modes 5 t Ex.: sum up array of n_m:.word 5! Size of array a_m:.word 4,2,5,8,3! 5 word array sum_m:.word 0! Sum of elements b_m:.skip 5*4! another 5 word array.text clr %r2! r2 will hold sum set n_m, %r3! r3 points to n ld [%r3], %r3! r3 gets array size set a_m, %r4! r4 points to array a loop:ld [%r4], %r5! Load element of a into r5 add %r5, %r2, %r2! sum = sum + element add %r4, 4, %r4! Incr ptr by word size subcc %r3, 1, %r3! Decrement counter bg loop! Loop until count = 0 nop! Branch delay slot set sum_m, %r1! r1 points to sum st %r2, [%r1]! Store sum ta 0! done a_m a_m+4 a_m+8 a_m+12 a_m+16 r2 r3 r4 r5 loop loop+1 loop+2 loop+3 loop+4 5 n_m a_m a_m+4 a_m+8 a_m+12 a_m+16 sum_m

144 CSE Addressing Modes 6 C-style example of pointer data type charx;// object of type character char *ptr;// pointer to character type ptr = &x;// ptr has address of x (points to x) *ptr = a;// store a at address in ptr Assembly language x_m:.byte 0 ! reserve character space; x_m = &x; [x_m] = x.align 4 ! align to word boundary ptr_m:.word 0 ! pointer variable; [ptr_m] = ptr.text set x_m, %r1! get address x_m into %r1 set ptr_m, %r2! get address ptr_m into %r2 st %r1, [%r2]! make [ptr_m] point to [x_m] set a, %r3! put character a into r3 set ptr_m, %r2! get address ptr_m into %r2 ld [%r2], %r1! get address [ptr_m], i.e. x_m, into %r1 stb %r3, [%r1]! store a at address [ptr_m], i.e., ptr x_m ptr_m a a x_m, i.e., addr of x x_m: ptr_m: r1 r2 r3

145 CSE Addressing Modes 7 –Register Indexed addressing t Suitable for accessing successive elements of the same type in a data structure. Ex.: Swap elements A[i] and A[k] in array t Effective address calculations! A A+4 A+8 A A r2 r3 r4 r7 r8 after sll <-

146 CSE Addressing Modes 8 t Simulating Register Indirect addressing on SPARC –SPARC doesn't truly have register indirect addressing. We can write st %r2, [%r1] but assembler converts this automatically into st %r2, [%r1+%r0] t Array mapping functions: used by compilers to determine addresses of array elements. Must know upper bound, lower bound, and size of elements of array. –Total storage = (upper - lower + 1)*element_size –Address offset for element at index k = (k - lower)*element_size –Address (byte) offset for A[3] = (3-0)*4 = 12 –This is for 1 dimensional arrays only!

147 CSE Addressing Modes 9 t 1D array mapping functions: Want an array of n elements, each element is 4 bytes in size, array starts at address arr. –Total storage is 4n bytes –First element is at arr+0 –Last element is at arr+4(n-1) –k th (k can range from 0…n-1) element is at arr+4k. Array uses zero-based indexing.

148 CSE Addressing Modes 10 t 2D array mapping functions: must linearize the 2D concept; e.g., map the 2D structure into 1D memory. –Convert into 1D array in memory

149 CSE Addressing Modes 11 t 2 ways to convert to 1D –Row major order (Pascal, C, Modula-2) stores first by rows, then by columns. E.g., –Column major order (FORTRAN) stores first by columns then by rows. E.g., –Row major 2D array mapping function: Given an array starting at address arr that is x rows by y columns, each element is m bytes in size, and indices start at zero, then element (i, j) may be found at location: arr + (y i + j) m

150 CSE Addressing Modes 12 t 3D array mapping function: natural extension of 2D function. Store by row, then column, then depth. –Array starting at arr with x rows, y columns, depth z, m element size. Element (i, j, k) is found at location: arr + (z y i + j) + k) m 1,0,

151 CSE Addressing Modes 13 CALCULATE: total storage offset for A(i,j,k) address for A(i,j,k) 1D2D3D element size (#bytes)421 # rows (x)733 # cols (y)155 # depth (z)112 starting addr (0)4812 i=110 j=011 k=001

152 CSE Addressing Modes 14 ! Example that adds 1 to every element of columns 1 and 2, not 0, of a 5 by 3 rows, 5 ! define symbolic constants.set cols, 3 arr_m:.skip rows * cols * 4! allocate space (.skip 60 same).text... setarr_m, %r3! get address of array clr%r1! %r1 is i (row) loop1:cmp%r1, rows! done if i >= rows bgedone nop set1, %r2! %r2 is j (col); start at one (skip col zero) loop2: cmp%r2, cols! if at last column, done with row bgeinc1 nop umul%r1, cols, %r4! # elements to skip for current row add%r4, %r2, %r4! then which column being accessed umul%r4, 4, %r4 ! change from element to byte offset ld[%r3+%r4], %r5! get arr[i][j] add%r5, 1, %r5 ! add 1 to the element value st%r5, [%r3+%r4]! store it back to arr[i][j] inc2:add%r2, 1, %r2 ! next column baloop2! continue inner loop over columns nop inc1:inc%r1 ! next row baloop1! continue outer loop over rows nop done:...

153 CSE Addressing Modes 15 –Displacement Addressing t Suitable for accessing the individual fields of record data structures. Each field can be of a different type. Use.set directive to establish offsets to fields within records. Then use displacement addressing to access those fields.

154 CSE Addressing Modes 16 t Ex.: Add 1 to the age field in a person record t Problem: alignment in memory. May have to waste some space in the person record in order to have the integer fields align on a word boundary.

155 CSE Addressing Modes 17 –Auto-increment and Auto-decrement addressing t SPARC does not support these modes. They may be simulated using register indirect addressing followed by an add or subtract of the size of the element on that register. t Useful for traversing arrays forward (auto-increment) and backward (auto-decrement). Also useful for stacks and queues of data elements.

156 CSE Subroutines 1 –Subroutines and subroutine linkage t Subroutines: programming mechanism to facilitate repeated computations and modularization. –Use of subroutines t Basis for structured and disciplined programming t Compact code (no need to write monolithic loops) t Relatively easy to debug (no cut-and-paste errors) t Requires little hardware support, mostly protocols and conventions to handle parameters.

157 CSE Subroutines 2 –Terminology t Caller: the code (which could be a subroutine itself) which invokes the subroutine of interest t Callee: the subroutine being invoked by the caller t Function: subroutine that returns one or more values back to the caller and exactly one of these values is distinguished as the return value t Return value: the distinguished value returned by a function

158 CSE Subroutines 3 –Terminology (continued) t Procedure: a subroutine that may return values to the caller (through the subroutines parameter(s)), but none of these values is distinguished as the return value t Return address: address of the subroutine call instruction t Parameters: information passed to/from a subroutine (a.k.a. arguments) t Subroutine linkage: a protocol for passing parameters between the caller and the callee

159 CSE Subroutines 4 –Subroutine linkage t Calling a subroutine –Assembly language syntax for calling a subroutine call label nop –Must change the program counter (as in a branch instruction) however, we must also keep track of where to resume execution after the subroutine finishes. Call instruction handles this atomically (i.e., without interruption) by: %r15 #PC (PC #nPC) nPC label t Returning from a subroutine –Assembly language syntax for returning from a subroutine retl nop

160 CSE Subroutines 5 t Returning from a subroutine (continued) –Again, must change the program counter to return to an instruction after the one that called the subroutine. The address of the instruction that called it was saved in %r15, and we must skip over the branch delay slot as well. So, this is accomplished by: nPC %r15+8 t Parameter passing: 2 approaches –Register based linkage: pass parameters solely through registers. Has the advantage of speed, but can only pass a few parameters, and it wont support nested subroutine calls. Such a subroutine is called a leaf subroutine. –Stack based linkage: pass parameters through the run-time stack. Not as fast, but can pass more parameters and have nested subroutine calls (including recursion).

161 CSE Register-based Linkage 1 –Subroutine linkage : t Startup Sequence: load parameters and return address into registers, branch to subroutine. t Prologue: if non-leaf procedure then save return address to memory, save registers used by callee. t Epilogue: place return parameters into registers, restore registers saved in prologue, restore saved return address, return. t Cleanup Sequence: work with returned values

162 CSE Register-based Linkage 2 –Example: Print subroutine..text main:set1, %r1! Initialize r1 and r2 set3, %r2 mov%r1, %r8! Print %r1 callprint nop mov%r2, %r8! Print %r2 callprint nop add%r1, %r2, %r8! Do our calculation callprint! Print the result (expect 4) nop ta0 print:set0, %r1! Ascii value of zero or%r8, %r1, %r2! Treat r8 as parameter mov%r2, %r8! Move into output register ta1! Output character mov\n, %r8 ta1! Output end of line (newline) retl! Return nop t Whats wrong with the above code?

163 CSE Register-based Linkage 3 –Which registers can leaf subroutines change? t Convention for optimized leaf procedures: t The subroutine must not use the value in any other register except to save it to memory somewhere and restore it before returning to the caller. t Problem: how can a subroutine call another subroutine? How can a subroutine call itself?

164 CSE Register-based Linkage 4 –Example: procedure to print linked list of ints. nop

165 CSE Parameter Passing 1 –Review of parameter passing mechanisms: t Pass by value copy: parameters to subroutine are copies upon which the subroutine acts. t Pass by result copy: parameters are copies of results produced by the subroutine. t Pass by reference copy: parameters to subroutine are (copies of) addresses of values upon which the subroutine acts. Callee is responsible for saving each result to memory at the location referred to by the appropriate parameter. t Hybrid: some parameters passed by value copy, some by result copy, and/or some by reference copy. Callee is responsible for saving results for reference parameters.

166 CSE Parameter Passing 2 –Parameter passing notes: t Array or record parameters typically are passed by reference copy (efficiency reasons). Primitive data types may be passed either way. t Conventions among languages allows any language to call functions in any other language: –Pascal: VAR parameters are passed by reference copy; all others are passed by value copy. –C: all parameters are passed by value copy. Must explicitly pass a pointer if you want a reference parameter. –C++: like Pascal, can pass by value or reference copy. –FORTRAN: all things passed by reference copy (even constants). –ADA: pass by value/result copy.

167 CSE Parameter Passing 3.text ! Example 10.1 of Lab Manual ! pr_str – print a null terminated string ! Parameters: %r8 – pointer to string (initially) ! ! Temporaries: %r8 – the character to be printed ! %r9 – pointer to string ! pr_str: mov %r8, %r9 ! we need %r8 for the ta 1 below pr_lp: ldub [%r9], %r8 ! load character cmp %r8, 0 ! check for null be pr_dn nop ta 1 ! print character ba pr_lp inc %r9 ! increment the pointer (in ! branch delay slot) pr_dn: retl nop

168 CSE Parameter Passing 4 t Summary from text (p. 220) –Pass by value copy: For small in parameters. Subroutines cannot alter the originals whose copies are passed as parameters. –Pass by value/result copy: For small in/out parameters. Callers cleanup sequence stores values of any in/out parameters. –Pass by reference copy: for in/out parameters of all sizes, and large in parameters. Out values are provided by changing memory at those addresses. (Note: pass by reference copy is passing an address by value copy.)

169 CSE Parameter Passing 5 –Write Sparc code for the caller and callee for the following subroutine using register based parameter passing ! global_function Integer subchr (A, B, C) ! Substitutes character C for each B in string [A], ! and returns count of changes. ! ! // In comments, "[A+index]" is denoted by "ch". ! index = 0 ! count = 0 ! LOOP: if [A+index]=0 go to END // while (ch != 0) { ! if [A+index] B go to INC // if (ch == B) { ! [A+index]=C // ch = C; ! count=count+1 // count++; } ! INC: index=index+1 // index++; ! go to LOOP // } !! data section C_m:.byte I ! parameter C B_m:.byte i ! parameter B A_m:.asciz "i will tip"! parameter A.align 4 R_m:.word 0! for storing result count Assume

170 CSE Stack-based Linkage 1 u Stack based linkage –Advantages t Permits subroutines to call others. t Allows a larger number of parameters to be passed. t Permits records and arrays to be passed by value copy. t Saving of registers by callee is built-in. t A way for callee to reserve memory for other uses is built-in, too. –Disadvantages t Slower than register based t More complex protocol –Why a stack? t Subroutine calls and returns happen in a last-in first-out order (LIFO). Also known as a runtime stack, parameter stack, or subroutine stack.

171 CSE Stack-based Linkage 2 t Items saved on the stack in one activation record –Parameters to the subroutine –Old values of registers used in the subroutine –Local memory variables used in subroutine –Return value and return address Say A() calls B(), B() calls C(), and C() calls A()

172 CSE Stack-based Linkage 3 –Stack based linkage parameter passing convention t Startup sequence: –Push parameters –Push space for return value t Prologue –Push registers that are changed (including return address) –Allocate space for local variables t Epilogue –Restore general purpose registers –Free local variable space –Use return address to return t Cleanup Sequence –Pop and save returned values –Pop parameters

173 CSE Stack-based Linkage 4 –Stack based parameter passing example: Register %r14 %sp stack pointer –Invariant: Always indicates the top of the stack (it has the address in memory of the last item on stack, usually a word). –Moved when items are pushed onto the stack. –Due to interruptions (system interrupts (I/O) and exceptions), values stored above %sp (at addresses less than %sp) can change at any time! Hence, any access above %sp is unsafe! Register %r30 %fp frame pointer –Indicates the previous stack pointer. Activation record is from (some subroutine-specific number of words before) the %fp to the %sp. –Invariant: %fp is constant within a subroutine (after prologue).

174 CSE Stack-based Linkage 5 –Stack based parameter passing example: t Want to implement the following subroutine (also a caller): ! global_function Integer subchr (A, B, C) ! Substitutes character C for all B in string A, ! and returns count of changes. ! ! // In comments, "*(A+index)" is denoted by "ch". ! index = 0 ! count = 0 ! LOOP: if *(A+index)=0 go to END // while (ch != 0) { ! if *(A+index) B go to INC // if (ch == B) { ! *(A+index)=C // ch = C; ! count=count+1 // count++; } ! INC: index=index+1 // index++; ! go to LOOP // } !! data section C_m:.byte I ! parameter C B_m:.byte i ! parameter B A_m:.asciz "i will tip"! parameter A.align 4 R_m:.word 0! for storing result count

175 CSE Stack-based Linkage! data section C_m:.word I ! parameter C B_m:.word i ! parameter B A_m:.asciz "i will tip"! parameter A.align 4 ! align to word address stack:.skip 250*4! allocate 250 word stack bstak: ! point to bottom of stack R_m:.word 0! reserve for count.text ! Programs one-time initialization start: set bstak, %sp! set initial stack ptr mov %sp, %fp! set initial frame ptr ! STARTUP SEQUENCE to call subchr() sub %sp, 16, %sp! move stack ptr set A_m, %r1! A is passed by reference st %r1, [%sp+4]! push address on stack set B_m, %r1! B is passed by value ld [%r1], %r1! get value of B st %r1, [%sp+8]! push parameter B on stack set C_m, %r1! C is passed by value ld [%r1], %r1! get value of C st %r1, [%sp+12]! push parameter C on stack ! SUBROUTINE CALL call subchr! make subroutine call nop! branch delay slot ! CLEANUP SEQUENCE ld [%sp], %r1! pop return value off stack add %sp, 16, %sp! pop stack set R_m, %r2! get address of R st %r1, [%r2]! store R...! the rest of the program Return value b stack: %sp -> %fp -> addr (a) c

176 CSE Stack-based Linkage 7 ! SUBROUTINE PROLOGUE subchr: sub %sp, 32, %sp! open 8 words on stack st %fp, [%sp+28]! Save old frame pointer add %sp, 32, %fp! old sp is new fp st %r15, [%fp-8]! save return address st %r8, [%fp-12] ! Save gen. Register … ! Save r9-r13, omitted ! SUBROUTINE BODY ld_reg: ld [%fp+4], %r8! pop (load) addr of A ld [%fp+8], %r9! pop (load) value of B ld [%fp+12], %r10! pop (load) value of C clr %r12! count clr %r13! index loop: ldub [%r8+%r13], %r11! load a string chr cmp %r11, 0x0! is chr=null? be done! then go to done cmp %r11, %r9! is chr<>B? (branch delay) bne inc! then go to inc nop! branch delay slot stb %r10, [%r8+%r13] ! change chr to C add %r12, 1, %r12! increment count inc: add %r13, 1, %r13! increment index ba loop! do next chr nop! branch delay slot done: st %r12, [%fp+0]! push (store) count on stack ! EPILOGUE … ! Restore r9-r13, omitted ld [%fp-12], %r8 ! Restore r8 ld [%fp-8], %r15! get saved return address ld [%fp-4], %fp! Get old value of frame ptr add %sp, 32, %sp! Restore stack pointer retl! return to caller nop! branch delay slot c b addr (a) %sp -> %fp -> return addr old frame ptr Return value... %r9 %r8

177 CSE Stack-based Linkage 8 u General Guidelines –Keep Startups, Cleanups, Prologues, and Epilogues standard (but not necessarily identical); easy to cut, paste, and modify. –Caller: leave space for return value on the TOP of the stack. –Callee: always save and restore locally used registers. –Pass data structures and arrays by reference, all others by value (efficiency).

178 CSE Our Fourth Example Architecture u Motorola M68HC11 u Called HC11 for short u Used in ECE 567, a course required of CSE majors u References: –Data Acquisition and Process Control with the M68HC11 Microcontroller, 2nd Ed., by F. F. Driscoll, R. F. Coughlin, and R. S. Villanucci, Prentice-Hall, –http://www.cse.ohio-

179 CSE Another Reference u Late in an academic term (such as now), you can hope to access on-line lecture notes from the Electrical and Computer Engineering course, ECE 265. u Visit u Under Academic Program, click on the link ECE Course Listings. u Find 265 and click on the link Syllabus of this quarter.

180 CSE HC11 compared with Sparc (1) HC11Sparc CISCRISC, Load/Store Instruction encoding lengths vary (8 to 32 bits) Instruction encoding lengths constant (32 bits) About 316 instructionsAbout 175 instructions 4 16-bit user registers, one of which is divided into two 8- bit registers bit user integer registers

181 CSE HC11 compared with Sparc (2) HC11Sparc 8-bit data bus32-bit data bus 16-bit address bus32-bit address bus 8-bit addressable Instruction execution not overlapped Instruction execution overlapped in a pipeline

182 CSE HC11 compared with Sparc (3) u A Strange Fact: The HC11 architecture allows accessing an operand from an external memory location with no execution-time penalty. [p. 27, M68HC11 Processor Manual, ] u Reason: The HC11 requirements state that the CPU cycle must be kept long enough to accommodate a memory access within one cycle. This seeming miracle is accomplished by keeping processor speed slow enough.

183 CSE HC11 Programmers Model (1) Accumulator AAccumulator B Accumulator D X Index Register Y Index Register Stack Pointer (SP) Program Counter (PC)

184 CSE HC11 Programmers Model (2) Condition Code Register (CCR) S X HI N ZVC Carry/Borrow Overflow Zero Negative I Interrupt Mask Half-Carry X Interrupt Mask Stop

185 CSE HC11 Assembly Language Format (1) u Like Sparc, it is line-oriented. u A line may: –Be blank (containing no printable characters), –Be a comment line, the first printable character being either a semicolon (;) or an asterisk (*), or –Have the following format ([] means an optional field): [Label] Operation [Operand field] [Comment field]

186 CSE HC11 Assembly Language Format (2) u Label: –begins in column 1, ending either with a space or a colon (:) –Contains 1 to 15 characters –Case sensitive –The first character may not be a decimal digit (0-9) –Characters may be upper- or lowercase letter, digits 0- 9, period (.), dollar sign ($), or underscore (_)

187 CSE HC11 Assembly Language Format (3) u Operation: –Cannot begin in column 1 –Contains: t Instruction mnemonic, t Assembler directive, or t Macro call (we havent studied macro expansion in this course) u Operand field: –Terminated by a space or tab character, –So multiple operands are separated by commas (,) without using any spaces or tabs

188 CSE HC11 Assembly Language Format (4) u Comment field: –Begins with the first space character following the operand field (or following the operation, if there is no operand field) –So no special printable character is required to begin a comment field –But it appears to be conventional to begin a comment field with a semicolon (;)

189 CSE Prefixes for Numeric Constants EncodingHC11Sparc DecimalNo symbol Hexadecimal$0x Binary%0b

190 CSE Assembler Directives (1) MeaningHC11Sparc Set location counter (origin) or.text End of sourceENDDoesnt have Equate symbol to a value EQU.set Form constant byteFCB.byte

191 CSE Assembler Directives (2) MeaningHC11Sparc Form double byteFDB.half Form character string constant FCC.ascii Reserve memory byte or bytes RMB.skip

192 CSE HC11 Addressing Modes u Immediate (IMM) u Extended (EXT) u Direct (DIR) u Inherent (INH) u Relative (REL) u Indexed (INDX, INDY)

193 CSE Immediate (IMM) u Assembler interprets the # symbol to mean the immediate addressing mode u Examples –LDAA#10 –LDAA#$1C –LDAA#%11100 –LDAA#C –LDAA#LABEL

194 CSE Extended (EXT) u Lack of # symbol indicates extended or direct addressing mode. These are forms of memory direct addressing, like SAM. u Extended means full 16-bit address, whereas Direct means directly to a low address, specified using only the least significant 8 bits of the address. u Examples –LDAA$2025 –LDAALABEL

195 CSE Direct (DIR) u Examples –LDAA$C2 –LDAALABEL

196 CSE Inherent (INH) u All operands are implicit (i.e., inherent in the instruction) u Examples: ABA, SBA, DAA u ABA means add the contents of register B to the contents of A, placing the sum in A (A + B A) u SBA means A – B A u DAA means to adjust the sum that got placed in A by the previous instruction to the correct BCD result; e.g., $09 + $26 yields $2F in A, then DAA changes this to $35.

197 CSE Relative (REL) u Used only for branch instructions u Relative to the address of the following instruction (the new value of the PC) u Signed offset from -128 to +127 bytes u Examples –BGE-18 –BHS27 –BGTLABEL

198 CSE Indexed (INDX, INDY) u Uses the contents of either the X or Y register and adds it to a (positive, unsigned) offset contained in the instruction to calculate the effective address u Example –LDAA4,X

199 CSE Interrupts u When an interrupt is acknowledged, the CPUs hardware saves the registers contents on the stack. An interrupt service routine ends with a(n) RTI instruction. This instruction automatically restores the CPU register values from the copies on the stack.

200 CSE Condition Code Register (CCR) u Its reasonably safe to say that every instruction that changes a register (A, B, D, X, Y, SP) affects the CCR appropriately. Unlike Sparc, there are no arithmetic instructions that do not set condition codes. u There do exist instructions that compare a register to a memory location by subtracting the memory contents from the register and throwing the result away, but setting the CCR (CMPA, CMPB, CPD, CPX, CPY).

201 CSE Example HC11 Program u Problem: Produce the following waveforms on the three least significant bits (LSBs) of parallel 8-bit output Port B (mapped to $1004), where we name the bits X, Y, and Z in increasing order of significance (X is bit 0; Y is bit 1; Z is bit 2). 10 ms 20 ms 15 ms X Y Z

202 CSE Example Source File, p. 1 STACK: EQU $00FF; set stack pointer PORTB: EQU $1004 ; set address of Port B ORG 0 DELAY1: FCB 10 ; set the waveform times DELAY2: FCB 20 ; for X, Y, and Z DELAY3: FCB 15

203 CSE Example Source File, p. 2 ORG $E000; program starts at $E000 MAIN: LDS #STACK ; initialize stack pointer L0: LDAA #1 ; set X on Port B to 1 STAA PORTB LDAB DELAY1 ; delay for 10 ms L1: JSR DELAY_1MS DECB BNE L1

204 CSE Example Source File, p. 3 LDAA #% ; set Y on Port B to 1 STAA PORTB LDAB DELAY2 ; delay for 20 ms L2: JSR DELAY_1MS DECB BNE L2 LDAA #% ; set Z on Port B to 1 STAA PORTB LDAB DELAY3 ; delay for 15 ms L3: JSR DELAY_1MS DECB BNE L3 BRA L0 ; continue to cycle

205 CSE Example Source File, p. 4 DELAY_1MS: PSHB ; subr. to delay for 1 ms LDAB #198 DELAY: DECB BRN DELAY NOP BNE DELAY PULB RETURN: RTS ORG $FFFE ; initialize reset vector RESET: FDB MAIN END

206 CSE Traps and Exceptions 1 u Traps, Exceptions, and Extended Operations –Other side of low level programming -- the interface between applications and peripherals –OS provides access and protocols

207 CSE Traps and Exceptions 2 –BIOS: Basic Input/Output System t Subroutines that control I/O t No need for you to write them as application programmer t OS interfaces application with BIOS through traps (extended operations (XOPs))

208 CSE Traps and Exceptions 3 –Where are OS traps kept? Two approaches: t Transient monitor: traps kept in a library that is copied into the application at link-time t Resident monitor: always keep OS in main memory; applications share the trap routines. t OS routines monitor devices. Frequently used routines kept resident; others loaded as needed.

209 CSE Traps and Exceptions 4 –(Assuming a res. monitor) How to find I/O routines? Store routines in memory, and make a call to a hard address. E.g., call 256 –When new OS is released, need to recompile all application programs to use different addresses. t Use a dispatcher –Dispatcher is a subroutine that takes a parameter (the trap number). Dispatcher knows where all routines actually are in memory, and makes the branch for you. Dispatcher subroutine must always exist in the same location. 2

210 CSE Traps and Exceptions 5 t Use vectored linking –Branch table exists at a well known location. The address of each trap subroutine is stored in the table, indexed by the trap number. –On RISC, usually about 4 words reserved in the table. If the trap routine is larger than 4 words, can call the actual routine.

211 CSE Traps and Exceptions 6 –Levels of privilege t Supervisor mode - can access every resource t User mode - limited access to resources t OS routines operate in supervisor mode, access is determined by bit in PSW (processor status word). XOP (books notation) can always be executed, sets privilege to supervisor mode ( ta ) RTX (books notation) can only be executed by the OS, and returns privilege to user mode ( rett ) –Exceptions t Caused by invalid use of resource. E.g., divide by zero, invalid address, illegal operation, protection violation, etc.

212 CSE Traps and Exceptions 7 t Control transferred automatically to exception handler routine. Similar to trap or XOP transfer. t Exceptions vs. XOPs –XOPs explicit in code, exceptions are implicit –XOPs service request and return to application; exceptions print message and abort (unless masked). –Trap example: non-blocking read ta 3 t If there is nothing in the keyboard buffer, return with a message that nothing is there. Otherwise, put the character into register 8.

213 CSE Traps and Exceptions 8 t Status of the keyboard is kept in a memory location, as is the (one-character) keyboard buffer. Memory mapped devices. t On SPARC, trap table has 256 entries are reserved for exceptions and external interrupts are used for XOPs. Trap table begins at address 0x0000. Each entry is 4 instructions (16 bytes) long.

214 CSE Traps and Exceptions 9 t Trap execution: ta 3 –Calculate trap address: 3 * x0800 = 16 * (3 + 0x080) –Save nPC and PSW to memory SPARC uses register windows Assumes local registers are available –Set privilege level to supervisor mode –Update PC with trap address (and make nPC = PC + 4) (jumps to trap table) –Trap table has instruction ba ta3_handler –rett Restores PC (from saved nPC value) and PSW (resets to user mode) Returns to application program

215 CSE Programmed I/O 1 u Programmed I/O –Early approach: Isolated I/O t Special instructions to do input and output, using two operands: a register and an I/O address. t CPU puts device address on address bus, and issues an I/O instruction to load from or store to the device.

216 CSE Programmed I/O 2 Isolated I/O

217 CSE Memory Mapped I/O t No special I/O instructions. Treat the I/O device like a memory address. Hardware checks to see if the memory address is in the I/O device range, and makes the adjustment. t Use high addresses (not real memory) for I/O memory maps. E.g., 0xFFFF0000 through 0xFFFFFFFF. CPU Memory I/O addr bus data bus read/write

218 CSE Programmed I/O 3 –Advantages of each t Memory mapped: reduced instruction set, reduced redundancy in hardware. t Isolated: dont have to give up memory address space on machines with little memory

219 CSE Programmed I/O - UARTs t UARTs –Universal Asynchronous Receiver Transmitter –Asynchronous = not on the same clock. –Handshake coordinates communication between two devices. –A kind of programmed I/O. KeyboardUART CPU serial parallel

220 CSE UARTs 1 u UART registers –Control: set up at init, speed, parity, etc. –Status: transmit empty, receive ready, etc. –Transmit: output data –Receive: input data –All four needed for bi- directional communications, –Status/control, transmit / receive often combined. Why? Control Reg Status Reg Transmit Reg Receive Reg Transmit Logic Receive Logic Control bus Address bus Data bus

221 CSE UARTs 2 u Memory mapped UARTs –Both memory and I/O listen to the address bus. The appropriate device will act based on the addresses. –Keyboards and Printers require three addresses (when addresses are not combined). –Modems require four. –(why?) UART 1 data UART 1 status UART 1 control UART 2 xmit UART 2 recv UART 2 status UART 2 control UART 3 xmit FFFF 0000 FFFF 0004 FFFF 0008 FFFF 000C FFFF 0010 FFFF 0014 FFFF 0018 FFFF 001C CPU MemoryUART1UART2 Control bus Address bus Data bus and so on

222 CSE Programmed I/O 4 u Programmed I/O Characteristics: –Used to determine if device is ready (can it be read or written). –Each device has a status register in addition to the data register. –Like previous trap example, must check status before getting data. –Involves polling loops.

223 CSE Programmed I/O – Polling Ex.: ta 2 handler (blocking keyboard input) u Cant afford to wait like this. Computer is millions of times faster than a typist. Also, multi-tasking operating systems cant wait. u Special purpose computers can wait. E.g., microwave oven controllers. u Must have a better way! Interrupts are the answer! Are you ready?... Are you ready now?... How about NOW?... Nope.. Not yet.. Hang on..

224 CSE Interrupts and DMA transfers 1 u Programmed (polled) I/O used busy waiting. –Advantages: simpler hardware –Disadvantages: wastes time u Interrupts (IRQs on PCs) –I/O device requests service from CPU. –CPU can execute program code until interrupted. Solves busy waiting problems. –Interrupt handlers are run (like traps) whenever an interrupt occurs. Current application program is suspended.

225 CSE Interrupts and DMA transfers 2 u Servicing an interrupt –I/O controller generates interrupt, sets request line high. –CPU detects interrupt at beginning of fetch/execute cycle (for interrupts between instructions). –CPU saves state of running program, invokes intrpt. handler. –Handler services request; sets the request line low. –Control is returned to the application program. Application Program : *Interrupt Detected* : Interrupt Handler Service Request : Clear Interrupt

226 CSE Interrupts and DMA transfers 3 u Changes to fetch/execute cycle u Problems –Requires additional hardware in Timing & Control. –Queuing of interrupts –Interrupting an interrupt handler (solution: priorities and maskable interrupts) –Interrupts that must be serviced within an instruction –How to find address of interrupt handler Interrupt Pending? Save PC Save PSW PSW=new PSW PC=handler_addr PC -> bus load MAR INC to PC load PC YN

227 CSE Interrupts and DMA transfers 4 u Example: interrupt driven string output –Want to print a string without busy waiting. –Want to return to the application as fast as possible Im ready!

228 CSE Trap handler implementation u Install trap handler into trap table –Buffer is like circular queue –only outputs, at most, one character disp_buf:.skip 256 ! buffers string to print disp_frnt:.byte 0 ! offset to front of queue disp_bck:.byte 0 ! offset to back of queue ta_6_handler: ! Copy str from mem[%r8] to mem[disp_buf+disp_bck] ! Disp_back = (disp_back+len(str)) mod 256 ! If display is ready ! If first char is not null, then output it ! Disp_frnt = (disp_frnt+1) mod 256 rett ! Return from trap Disp_buf: disp_frnt disp_bck newest byte Undisplayed byte Oldest byte

229 CSE Interrupt handler implementation u This too outputs only one character at most, but when display becomes ready again, it generates another interrupt which invokes this routine! display_IRQ_handler: ! Save any registers used ! If disp_frnt != disp_bck (queue is not empty) ! Get char at mem[disp_frnt] ! If char is not null, then output it ! Disp_frnt = (disp_frnt+1) mod 256 ! Restore registers and set the request line low rett ! Return from trap u Uses the UART for transmission. Im ready! CPU Memory

230 CSE Interrupts and DMA transfers 5 u Problems with interrupt driven I/O t CPU is involved with each interrupt t Each interrupt corresponds to transfer of a single byte t Lots of overhead for large amounts of data (blocks of 512 bytes) MemoryCPU Device Controller Execute 10s or 100s of instructions per byte Transfer one word of data Interrupt Transfer one byte of data

231 CSE Interrupts and DMA transfers 6 u DMA (Direct Memory Access) t Want I/O without CPU intervention t Want larger than one byte data transfers t Solution: add a new device that can talk to both I/O devices and memory without the CPU; a specialized CPU strictly for data transfers. Memory CPU Device Controller DMA Controller

232 CSE Interrupts and DMA transfers 7 u Steps to a DMA transfer –CPU specifies a memory address, the operation (read/write), byte count, and disk block location to the DMA controller (or specify other I/O device). –DMA controller initiates the I/O, and transfers the data to/from memory directly –DMA controller interrupts the CPU when the entire block transfer is completed. u Problem –Conflicts accessing memory. Can either arbitrate access or get a more expensive dual ported memory system.

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