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Energy Efficient Designs with Wide Dynamic Range Vivek De Intel Fellow Director of Circuit Technology Research Circuits Research Lab Intel Labs.

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Presentation on theme: "Energy Efficient Designs with Wide Dynamic Range Vivek De Intel Fellow Director of Circuit Technology Research Circuits Research Lab Intel Labs."— Presentation transcript:

1 Energy Efficient Designs with Wide Dynamic Range Vivek De Intel Fellow Director of Circuit Technology Research Circuits Research Lab Intel Labs

2 2 2 Platform segment characteristics Few designs must serve all segments Server Desktop Mobile MID Power Workload Thermal V-F Cores Ambient Load High Med Low Very low Throughput Parallel HPC-RAS Burst Serial-Parallel Stream Graphics Med/High Wide Med/High Wide Med/High Wide Low/Med Wide SOC Active Fan (-less) Passive Fan-less High Wide Med-High Wide Med-High Wide Low-Med Wide Controlled Cool Controlled Varying Uncontrolled Extreme Uncontrolled Extreme Burst Serial-Parallel Stream Graphics Burst Serial-Parallel Stream Graphics

3 3 3 Dynamic platform control Deliver best user experience under constraints Dynamic V/F control Independent V/F control regions Workload-based core activation & shutdown Scenario-based power allocation Maximize performance & efficiency

4 4 4 Dynamic adaptation & reconfiguration Adapt & reconfigure for best power-performance Dynamic Control Unit Processor Aging Sensor Thermal Sensor Voltage Sensor Current Sensor Sensors Voltage Control Frequency Control Configuration Control Change V Change F Reconfigure

5 5 5 Resilient platforms Resiliency for performance, efficiency & reliability Circuit & Design Microarchitecture Microcode Firmware VM OS Programming System Applications Lower error rate Less recovery overhead Less silicon overhead Resiliency framework System adaptation System recovery Error correction Fault confinement Fault diagnosis Error detection System reconfiguration Resilient platform features

6 6 6 TFLOPS at 62 watts Coarse-grain management Slow voltage & frequency change Fine-grain management FUTURE Fine-grain power management Temporal domain Fast voltage & frequency change TODAY V/F change latency Active-sleep transition latency Wake-up latency Wake-up prediction State transition energy Supply noise

7 7 7 Fine-grain power management Spatial domain Same voltage to all cores Same frequency for all cores Coarse-grain management TODAY Each core/cluster at optimum voltage Each core/cluster at optimum frequency Fine-grain management FUTURE V/F domain interfaces Synchronization overhead Clock generation/distribution Power grid routing Optimum V/F for non-cores Sub-core clock/leakage gating

8 8 8 Advanced voltage regulators Area efficient Scalable Persistent rail Conversion Efficient Lower loss Higher fidelity Simpler Distribution Low loss Fast & efficient Load adaptive Independent rails Control Fine-grain VR innovations for fine-grain power management

9 9 9 Research testchip I/O Area PLL single tile 1.5mm 2.0mm TAP 21.72mm I/O Area PLL TAP 12.64mm

10 10 Many-core power management Dynamic sleep STANDBY: Memory retains data 50% less power/tile FULL SLEEP: Memories fully off 80% less power/tile 21 sleep regions per tile (not all shown) FP Engine 1 FP Engine 2 Router Data Memory Instruction Memory Memory FP Engine 1 Sleeping: 90% less power FP Engine 2 Sleeping: 90% less power Router Sleeping: 10% less power (stays on to pass traffic) Data Memory Sleeping: 57% less power Instruction Memory Sleeping: 56% less power Energy efficiency of 19.4 Gflops/Watt

11 11 Memory integration Processor with Cu bump Package Processor Memory 256 KB SRAM per core 4X C4 bump density 8490 thru-silicon vias Thru-Silicon Via 3D stacking with thru-silicon vias

12 12 Voltage-frequency range limiters Reliability & functional failures limit range Voltage Frequency Vmax Vmin Fmax Reliability Thermals Power delivery Vmax/Fmax limiters Circuit functional failures Soft errors Steep frequency roll-off Aging Vmin limiters

13 13 Voltage-frequency margins Voltage Frequency Voltage Frequency V margin IR drop Inductive droops Load line variations V variationT variation F margin Nominal T Worst T V margin F margin Voltage Frequency Voltage Frequency Aging Path activity BOL EOL V margin F margin Nominal Worst F margin V margin MIS Signal coupling Critical path

14 14 Array voltage Cumulative fail rate Nominal array Vmin Worst die Vmin SER, erratic bits Array Vmin Density Vmin 8T+ cell Multi-V 6T SRAM LLC density Multi-voltage cache

15 15 ReadWriteRetention NXWeakStrong- NPDStrongWeakBalanced PPUStrongWeakBalanced Dynamic multi-voltage cache 6T SRAM cell NX NPD PPU Wordline underdrive for read Dynamic voltage collapse for write 45nm dynamic multi-V testchip MIN cell 26X less fails Array to WL differential supply noise tracking Pulse width control Source: Intel

16 16 Reduce cache low V/F by eliminating failing words/bits Word disable Failing words Bitmap of failing words Bit fix 1-bit ECC Word disable Bit fix 10-bit ECC Vmin (mV) DensityCapacityLatency (cycles) IPCEPI Conventional 6601* (8-way) L1: 3 L2: 20 1* 32KB L1 Word disable (4-way) MB L2 Bit fix (6-way) * Normalized reference value Cache reconfiguration Source: Intel

17 17 Low-voltage logic design Narrow muxes No stack height > 2 Robust level converters Efficiency: MIPS/Watt Performance Improve range Impact max performance Robust flip-flops Efficiency: MIPS/Watt Performance Improve range & efficiency Design & technology optimizations to balance range, performance & efficiency

18 18 Low-voltage motion estimation engine 65nm CMOS 70K transistors Die area ~1mm 2

19 19 Dynamic V & F adaptation Adapt F/V to V/T change  reduce V/T margin Adapt F/V to aging  reduce aging margin Environment-aware dynamic adaptation Prototype chip in 90nm Source: Intel

20 20 Resilient circuits Detect errors in critical path FFs Propagate error signals Correct errors by re-execution Feedback to adaptive V/F Error Detection Sequential (EDS) 65nm resilient circuits testchip

21 21 Resiliency experiments Response to voltage droops Source: Intel

22 22 Summary Energy efficiency and wide dynamic operating range are critical for all platforms Integration, fine-grain power management, advanced voltage regulators & 3D memory stacking are key for energy efficiency Reliability, functionality, margins & efficiency limit dynamic operating range Multi-voltage design, dynamic adaptation, reconfiguration & resiliency are key enablers

23 23 Acknowledgement CRL prototypeBangalore DesignLTD DesignMurli Tirumala Tomm AldridgeMark AndersPaolo AseronRavi Mahajan Jerry BautistaNitin BorkarShekhar BorkarRavi Prasher Keith BowmanSaurabh DigheZeshan ChishtiVenkat Natarajan Lev FinkelsteinShih-Lien LuVarghese GeorgeAnand Deshpande Marci GlennGeorge GoodmanSteve GuntherAli Farhang Matthew HaycockChris WilkersonMing ZhangAmit Agarwal Andrew HenroidYatin HoskoteJason HowardRobert Chau Steven HsuTanay KarnikHimanshu KaulRajesh Kumar Alaa AlameldeenM. KhellahV. ErraguntlaKetan Paranjape Sean KoehlR. KrishnamurthyPartha KunduGreg Taylor Sanu MathewRandy MooneyA. RaychowdhuryP. Vishakantaiah Alon NavehTrang NguyenFabrice PailletR. Kuppuswamy Clark RobertsRonny RonenErfaim RotemRohit Vidwans Mark RowlandGreg RuhlGerhard SchromGautam Doshi Joe SchutzD. SomasekharJames TschanzSunit Tyagi Sriram VangalManny VaraHoward WilsonB. Chatterjee Bibiche GeuskensSteven HsuKevin ZhangSati Banerjee Clair WebbMark BohrGunjan Pandya

24 24 Q&A


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