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Chapter 9 Bootloader. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 2 Learning Objectives Need for a bootloader. Need.

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Presentation on theme: "Chapter 9 Bootloader. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 2 Learning Objectives Need for a bootloader. Need."— Presentation transcript:

1 Chapter 9 Bootloader

2 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 2 Learning Objectives Need for a bootloader. Need for a bootloader. What happens during a reset. What happens during a reset. Boot modes and processes. Boot modes and processes. Memory map. Memory map.

3 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 3 What is the bootloader? When the DSP is NOT powered or under reset the internal program memory is in a random state. When the DSP is NOT powered or under reset the internal program memory is in a random state. DMA L2 Cache L1P Cache L1D Cache CPU Boot Config EMIF EPROM C6211/C6711 VCC VCC Addr

4 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 4 What is the bootloader? When the DSP is powered and the CPU is taken out of reset the internal memory is still in a random state and the program will start running for address zero. When the DSP is powered and the CPU is taken out of reset the internal memory is still in a random state and the program will start running for address zero. DMA L2 Cache L1P Cache L1D Cache CPU Boot Config EMIF EPROM C6211/C6711 VCC VCC Addr PC=0000PC=0001PC=0002PC=

5 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 5 What is the bootloader? With the boot, a portion of code can be automatically copied from external to internal memory. With the boot, a portion of code can be automatically copied from external to internal memory. DMA L2 Cache L1D Cache CPU Boot Config EMIF EPROM C6211/C6711 VCC VCC L1P Cache

6 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 6 What happens at reset: System timeline When the device is held in reset: When the device is held in reset: The device is initialised to the default state. The device is initialised to the default state. Most 3-state outputs are in the high impedance state. Most 3-state outputs are in the high impedance state. Device Reset /RS pin CPU Reset

7 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 7 What happens at reset: System timeline On the rising edge of the /RS pin: On the rising edge of the /RS pin: The processor checks the boot mode configuration (HD[4:3]) and starts the boot loader. The processor checks the boot mode configuration (HD[4:3]) and starts the boot loader. The EDMA automatically copies 1K bytes from the beginning of CE1 location to the internal program memory starting at address zero. The EDMA automatically copies 1K bytes from the beginning of CE1 location to the internal program memory starting at address zero. Device Reset CPU Reset Boot load in operation /RS pin CPU Reset

8 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 8 What happens at reset: System timeline Once the boot loader has finished initialising the internal memory the CPU is taken out of reset. Once the boot loader has finished initialising the internal memory the CPU is taken out of reset. The CPU starts running from address zero. The CPU starts running from address zero. Device Reset CPU Reset Boot load in operation /RS pin CPU Reset

9 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 9 C6211 and C6711 Memory map The C6211 and C6711 has only one memory map, MAP0. The C6211 and C6711 has only one memory map, MAP0. Internal memory is always located at address zero. Internal memory is always located at address zero. Internal memory can be used as either program or data. Internal memory can be used as either program or data.

10 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 10 C6211 and C6711 Memory map

11 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 11 Boot modes and processes Two questions need to be answered about the bootloader, these are: Two questions need to be answered about the bootloader, these are: What methods of boot are available and how are they selected? What methods of boot are available and how are they selected? How does the DSP know what type of memory it is going to boot from? How does the DSP know what type of memory it is going to boot from?

12 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 12 Bootloader operational modes The TMS320C6211 and C6711 support the following boot configurations: The TMS320C6211 and C6711 support the following boot configurations: (1)Host Port Interface (HPI) boot. (2)8-bit ROM boot. (3)16-bit ROM boot. (4)32-bit ROM boot. Note: with the C6211 and C6711 there is no no-boot mode as for the other C6000 processors.

13 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 13 Bootloader configuration The boot mode is selected by pulling the HD[4:3] pins (HPI data bus pins) high or low at reset. The boot mode is selected by pulling the HD[4:3] pins (HPI data bus pins) high or low at reset. Depending on the voltages on this pins one of the four modes is selected. Depending on the voltages on this pins one of the four modes is selected. Boot mode HPI boot 8-bit ROM boot 16-bit ROM boot 32-bit ROM boot HD[4:3]

14 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 14 Endianess configuration The endian mode is determined at the same time as boot mode. The endian mode is determined at the same time as boot mode. Pulling pin HD[8] high or low selects the following endian modes. Pulling pin HD[8] high or low selects the following endian modes. Device operation Big endian Little endian HD[8] 01 Note: ensure that the software development tools are also configured with the same endian type as the hardware.

15 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 15 Clock mode configuration The input clock mode is also determined at the same time as boot mode. The input clock mode is also determined at the same time as boot mode. Pulling CLKMODE0 pin high or low selects the following modes. Pulling CLKMODE0 pin high or low selects the following modes. PLL frequency multiplier No multiplication Input frequency is multiplied by 4 CLKMODE0 01

16 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 16 Boot process: HPI boot mode In this mode the following sequence is used: In this mode the following sequence is used: The CPU is held in reset while the remaining of the device is released. The CPU is held in reset while the remaining of the device is released. The host processor initialises the CPUs memory space through the HPI. The host processor initialises the CPUs memory space through the HPI. When all the necessary memory is initialised the host processor takes the CPU out of reset by writing a 1 to the DSPINT bit filed of the Host Port Interface Control (HPIC) register. When all the necessary memory is initialised the host processor takes the CPU out of reset by writing a 1 to the DSPINT bit filed of the Host Port Interface Control (HPIC) register. DSPINT HPIC DSPINT HPIC 17 17

17 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 17 Boot process: HPI boot mode DMA L2 Cache L1D Cache CPU Boot Config EMIF DRAM C6211/C6711 /RS L1P Cache HPI HOST

18 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 18 Boot process: HPI boot mode Question: How does the host processor check that the memory has been initialised correctly? Question: How does the host processor check that the memory has been initialised correctly? Answer: The host can read and write to any address so it can check by reading the initialised memory. Answer: The host can read and write to any address so it can check by reading the initialised memory.

19 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 19 Boot process: HPI boot mode Question: If an external memory needs to be initialised via the HPI how do you ensure that the EMIF is set correctly? Question: If an external memory needs to be initialised via the HPI how do you ensure that the EMIF is set correctly? Answer: The first thing the Host should do is to write the EMIF register then write to the external memory locations. Answer: The first thing the Host should do is to write the EMIF register then write to the external memory locations.

20 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 20 Boot process: ROM boot mode In this mode the following sequence is used: In this mode the following sequence is used: The CPU is held in reset while the bootloader operates. The CPU is held in reset while the bootloader operates. The bootloader copies 1Kbytes from CE1 with the default settings to internal memory at address zero. The bootloader copies 1Kbytes from CE1 with the default settings to internal memory at address zero. CPU is taken out of reset. CPU is taken out of reset. CPU starts running code from address zero. CPU starts running code from address zero.

21 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Chapter 9, Slide 21 Boot process: ROM boot mode DMA L2 Cache L1D Cache CPU Boot Config EMIF DRAM C6211/C6711 /RS L1P Cache ROM VCC

22 Chapter 9 Bootloader - End -


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