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E E# A instrução – 0 dados - 1 ler – 1 escrever - 0 48 MHz.

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Presentation on theme: "E E# A instrução – 0 dados - 1 ler – 1 escrever - 0 48 MHz."— Presentation transcript:

1 E E# A instrução – 0 dados - 1 ler – 1 escrever MHz

2 G12 F13 F12 E14 E13 D15 D14 C16 LCD D(7:0) (H15,F16,H13) Address (2:0) G13G14 E E# D16 Read(1) Write(0) botões S 1...S 8 L 1 L 2 L 3 L 4 B4B4 B1B1 case idx is when 0=> ext_a<= "00" & rs; when 1=> cs <= '1';ext_d<= cmd; when 2=> cs <= '0'; when 3=> null; end case; 1. instrução/informação 2. dados 3. activar LCD 4. não faz nada

3 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity lcd is port ( clk48: in std_logic; rst: in std_logic; ext_a: out std_logic_vector(2 downto 0); ext_d: out std_logic_vector(7 downto 0); ext_rw: out std_logic; cs_lcd: out std_logic; csn_lcd: out std_logic); end lcd;

4 by Valery Sklyarov and Iouliia Skliarova -- DETUA, IEETA, Aveiro University, Portugal in this example a part of VHDL code from Trenz electronic was used Interaction with HD44780U Dot Matrix LCD controller/driver -- LCD 2 lines x 16 characters library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Hitachi_lcd is port ( clk48: in std_logic; -- clock 48 MHz rst: in std_logic; -- reset ext_a: out std_logic_vector(2 downto 0); -- LCD control ext_d: out std_logic_vector(7 downto 0); -- LCD data ext_rw: out std_logic; -- LCD read/write cs_lcd: out std_logic; -- LCD chip select active high csn_lcd: out std_logic -- LCD data direction ); end Hitachi_lcd;

5 architecture Behavioral of Hitachi_lcd is signal clk: std_logic;-- local clock signal div: unsigned (14 downto 0); -- local clock divider signal reset: std_logic;-- lcd reset sequence active signal cmd: std_logic_vector (7 downto 0);-- data/command to lcd signal rs: std_logic;-- register select bit for lcd signal idx: integer range 0 to 3;-- sequencer index for lcd timing signal cs: std_logic;-- chip select for lcd signal cnt: unsigned (5 downto 0);-- character, command counter constant line1: string(1 to 16):= "LCD operations :"; -- strings to display constant line2: string(1 to 4):= "DEMO"; begin process(clk48, rst)-- local clock generator begin if rst= '1' then div '0'); elsif rising_edge(clk48) then div<= div + 1; end if; end process; clk<= div(div'left);

6 process(clk, rst) -- LCD sub-clocks sequencer begin if rst= '1' then idx <= 0; elsif rising_edge(clk) then if idx= 3 then idx<= 0; else idx<= idx + 1; end if; end if; end process; process(clk, rst)-- LCD local control signals generator begin if rst= '1' then cs <= '0'; ext_a '0'); ext_d '0'); elsif rising_edge(clk) then case idx is when 0=> ext_a<= "00" & rs; -- set register address when 1=> cs <= '1';ext_d<= cmd; -- write data, activate chip select when 2=> cs <= '0'; -- deactivate chip select when 3=> null; -- data hold time end case; end if; end process; ext_rw<= '0';-- always write to LCD cs_lcd <= cs;-- chip select for LCD csn_lcd<= '0';-- always write to LCD

7 process(clk, rst) begin if rst= '1' then cmd<= x"02"; -- clear DDRAM counter, switch off shift rs<= '1'; reset<= '1';-- activate LCD initialization from the beginning cnt '0'); elsif rising_edge(clk) then if idx = 2 thencnt <= cnt + 1; end if; if (reset ='0') then-- normal functionality after initialization case cnt is when "000000" => cmd <= x"80"; rs <= '0';-- DDRAM address to the beginning of the first line when "000001" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(1)), 8)); rs <= '1'; when "000010" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(2)), 8)); rs <= '1'; when "000011" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(3)), 8)); rs <= '1'; when "000100" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(4)), 8)); rs <= '1'; when "000101" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(5)), 8)); rs <= '1'; when "000110" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(6)), 8)); rs <= '1'; when "000111" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(7)), 8)); rs <= '1'; when "001000" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(8)), 8)); rs <= '1'; when "001001" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(9)), 8)); rs <= '1'; when "001010" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(10)), 8)); rs <= '1'; when "001011" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(11)), 8)); rs <= '1'; when "001100" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(12)), 8)); rs <= '1'; when "001101" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(13)), 8)); rs <= '1'; when "001110" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(14)), 8)); rs <= '1';

8 when "001111" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(15)), 8)); rs <= '1'; when "010000" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(16)), 8)); rs <= '1'; when "010001" => cmd <= x"C0"; rs <= '0';-- DDRAM address to the beginning of the second line when "010-1-"|"0101--" => cmd <= x"20"; rs <= '1'; when "011000" => cmd <= std_logic_vector(to_unsigned(character'pos(line2(1)), 8)); rs <= '1'; when "011001" => cmd <= std_logic_vector(to_unsigned(character'pos(line2(2)), 8)); rs <= '1'; when "011010" => cmd <= std_logic_vector(to_unsigned(character'pos(line2(3)), 8)); rs <= '1'; when "011011" => cmd <= std_logic_vector(to_unsigned(character'pos(line2(4)), 8)); rs <= '1'; when "0111--"|"10000-" => cmd <= x"20"; rs <= '1'; when "100010" => cmd <= x"80"; rs <= '0'; when others => cmd <= x"80"; rs <= '0';--cnt <= "000000"; end case; else-- initialization of LCD from the beginning case cnt is-- delay such as from "000000" to "001000" is important -- for satisfying LCD timing requirements when "000000" => cmd <= x"38"; rs <= '0';-- (x"20" Function Set)|(x"10" 8-bit data)| -- (x"08" two lines) when "001000" => cmd <= x"0C"; rs <= '0'; -- (x"08" display control)|(x"04" display on)| -- (x"00" cursor off - our case; x"02" cursor on) when "010000" => cmd <= x"06"; rs <= '0';-- (x"04" entry mode set)|(x"02" increment on) when "011000" => cmd <= x"01"; rs <= '0';-- (x"01" clear display and DDRAM counter) when "100000" => reset <= '0'; cnt <= "000000"; -- initialization is finished when others => null; end case; end if; end process; end Behavioral;

9 VHDL Reserved Word: constant Purpose A class of data object. Constants can hold a single value of a given type. If the value is not specified, the constant is a deferred constant, and can appear inside a package declaration only. Syntax constant_declaration ::= constant identifier_list : subtype_indication [:= expression]; Example constant alpha : character := 'a'; Example, deferred constant constant no_of_outputs : integer; constant line1: string(1 to 16):= "LCD operations :"; -- strings to display

10 VHDL Reserved Word: null Purpose Sequential statement that causes no action to take place; execution continues with the next statement. Syntax null_statement ::= [label :] null; Example if (sum >= 100) then p1 : null B1111 – binary bit vector literal O353 – octal bit vector literal XA5 – hexadecimal bit vector literal

11 Scalar Types Enumerated Character (literals: 128 characters of the ASCII character set) Bit Boolean (literals: true, false) Severity_level (literals: note, warning, error, failure) Numeric Integer Physical Floating_point Signal attribute 'pos' indicates that unspecified logic should be given the value of 0. when "01111" => lcdout <= std_logic_vector(to_unsigned(character'pos(line2(1)), 8));

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