# Final Exam Review CSE 241 B.Ramamurthy 7/24/2018 B.Ramamurthy.

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Final Exam Review CSE 241 B.Ramamurthy 7/24/2018 B.Ramamurthy

Place and Time Date:4/18/2015, Friday Time: 7.15-10.15PM
Place: NSC 201 Please bring Pencils, pens and erasers, your ID Closed book exam 7/24/2018 B.Ramamurthy

Topics Chapter 4: Decoders and Multiplexers: pp.150-164 (4.9-4.11)
Chapter 4: Verilog Models of combinational circuit: Gate level modeling and behavioral modeling: Chapter 5: Sequential circuit analysis: pages Chapter 5: Synthesizable Verilog models of sequential circuits: pages , p Chapter 5: Sequential circuit design: p.236-p.245 All the homework problems Chapter 7: PLA arrays: given a combinational circuit spec, design PLA. 7/24/2018 B.Ramamurthy

How do I study? Help! Writing a test bench: pages , read every line of these pages, and understand Example 4.10 on p.181 From state diagram to Verilog simulation: see example on p.229, only state diagram based model and ONLY its test bench on the next page (p.230) Analysis example: see figure 5.18, table 5.4, up to figure 5.19 on p.214 and equations Design example; p : figure 5.27, table 5.11, figure 5.28, figure 5.29 What ever we discussed in class about Ch.7 7/24/2018 B.Ramamurthy

Format & possible questions
Design combinational circuits using decoders and mux Sequential circuit analysis Sequential circuit design Verilog HDL description and verification (means test bench included) of combinational circuits Verilog HDL description & verification of sequential circuits FPGA design 7/24/2018 B.Ramamurthy

Remember… Learn from the home works assigned
Find ways to efficiently answer questions Find ways to avoid silly mistakes Create a mental checklist to make sure you have not missed anything important on the exam (like your name of the exam paper!) Read the question paper and strategize on the order in which you will answer the questions Come prepared: there is no substitute for hard work Build up competencies and not deficiencies… Good luck. 7/24/2018 B.Ramamurthy

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