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Paris-LPNHE 10.10.12 ATLAS pixel1 CPPM ATLAS Pixel upgrade pour HL LHC LPNHE, Paris 10 octobre 2012 A.Rozanov.

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Presentation on theme: "Paris-LPNHE 10.10.12 ATLAS pixel1 CPPM ATLAS Pixel upgrade pour HL LHC LPNHE, Paris 10 octobre 2012 A.Rozanov."— Presentation transcript:

1 Paris-LPNHE ATLAS pixel1 CPPM ATLAS Pixel upgrade pour HL LHC LPNHE, Paris 10 octobre 2012 A.Rozanov

2 IBL construction and installation Paris-LPNHE ATLAS pixel2

3 IBL Stave-0 final qualification Stave=0 have been thermally qualified and is under Thermal and pressure cycles Stave TFOM is bellow 17°C cm 2 /W which is acceptable and within expected values Power up to 345W on a stave and system permit to maintain the sensor to -15°C which is a good input to prevent thermal runaway 3Paris-LPNHE ATLAS pixel Stave fully loaded with modules A-side C-side C- side

4 Cooling line prototyping Induction Brazing qualification for PP0 joint is ongoingInduction Brazing qualification for PP0 joint is ongoing Quality still OK, 40 sample brazed and tested: He leaks, visual, thermal shock Stave extension tests in October June 2013: andJune 2013: 14 staves should be assembled and having all components in hand for 14 staves commissioning. Sealing of the IBL volume for cold tests. PP0 Ti Sleeve PP1 Ti Fitting PP1 Electrical Break Induction Chamber Brazed joint metallurgical analysis 4Paris-LPNHE ATLAS pixel

5 LoI pixel layout Layout classique – Cylindres barrel et disques CS IN2P3 21 Juin 2012 First LoI-phase-II: présentation à AW, Montreux, Octobre 12 Final LoI phase-II: Janvier 2013 Paris-LPNHE ATLAS pixel5

6 Inner Pixels Option: Two IBL-like barrel layers A.Rozanov Montreux Tuned to Inner pixels R=4 cm and R=8 cm Compatible with clamp shell installation 0.55%X0 Bare stave %X0 support = 0.58% X0

7 Material per layer Component IBL-likeX0% Sensor 150um0.16 FE chip 100um0.11 Flex0.19 Cables0.29 Glue0.03 IBL like bare stave0.55 Support0.03 Total1.36 A.Rozanov Montreux Stave typeX0 Current pixel3.8% IBL1.7% ITK IBL-like1.36% ITK I-beam1.21%

8 Inner Pixels Front End FE-electronics with classical sensors, two main options: – 65 nm pixel 25x150 µm – 3D 130nm pixel 50x125 µm HV CMOS monolithic sensor+electronics 180nm HV2FEI4 ATLAS chip with capacitive coupling to FEI4 subpixel 33x125 µm More RD on different combinations of HV-HR CMOS, 65 nm, 3D Test of 65nm chip at CERN PS, excellent results for SEU tolerance, some concern on total dose in shift registers A.Rozanov Montreux nm prototype 65 nm test pixel matrix

9 Inner Pixels FE-electronics: 3D 130nm pixel 50x125 µm A.Rozanov Montreux HV2FEI4 demontrator

10 Inner Pixels 3D FE-electronics: FE-TC4-P1 test chip pixel 50x166 µm show good results A.Rozanov Montreux Digital tier Sthr=174e noise=42e - Analog tier Thr=2200e Sthr=150e noise=46e -

11 Inner Pixels HV CMOS monolithic sensor+electronics 180nm HV2FEI4 ATLAS chip with capacitive coupling to FEI4 subpixel 33x125 µm A.Rozanov Montreux Before irradiationHV2FEI4 demonstrator

12 HV2FEI4 reached already 375 MRads Despite degradations at high temperature (42 degC) chip is working Next round of cold tests at CERN PS at -10 deg C New more Rad Hard chip in November 2012 Paris-LPNHE ATLAS pixel12

13 IBL and outer ITK pixels FE-I4 Test of FE-I4-B SEU - confirms good resistance as expected Test of General ADC – works up to 375 Mrads Test of temperature sensor inside FE-I4-B – calibrate as a function of the dose Paris-LPNHE ATLAS pixel13

14 Paris-LPNHE ATLAS pixel14 ATLAS pixel upgrade pour HL LHC Responsabilités: Positionnement du CPPM A.Rozanov - chair Joint Pixel-IBL-IB, ITK-SC A.Rozanov - editor Pixel/Readout ITK LoI Phase-II E.Vigeolas - responsable stave IBL, SC E.Vigeolas - ITK local support group, backup document local support Lol Phase-II J.C.Clémens - coordination électronique 3D IN2P3 G.Hallewell - coordination group sonar ID M.Barbero - programme TALENT au CPPM

15 Paris-LPNHE ATLAS pixel15 CPPM: Management Plan de management: Responsabilités Stave IBL, Local support ITK - E.Vigeolas Sonar – Cooling - G.Hallewell Electronique, via last AIDA -J.C. Clémens FE-I4 - M.Menouni FE-TC4 - P.Pangaud 65 nm - M.Menouni HV-HR CMOS - P.Pangaud Stave -1 Wire Bonding

16 Paris-LPNHE ATLAS pixel16 CPPM: Ressources humaines TâchesNomCorpsService 3DJ.C.ClemensIRInst IBL stave, ITKE.VigeolasIRMec Tests FE-I4, TC4, 65nm etcP.BreugnonIRElec FE-I4, 65 nmM.MenouniIRElec 3D,HVCMOS,65nmP.PangaudIRElec HVCMOS, 65 nmS.GodiotIRElec FE-I4, C4-P3, 65 nmD.FougeronIEElec FE-I4, 65 nmF.GensolenIRElec Test 3D, HVCMOSF.BompardVitesseElec IBL stave, ITKF.RivièreAIMec 65nm SEU testM.JevaudIEElec Sonar, coolingG.HallewelIRInst

17 Paris-LPNHE ATLAS pixel17 CPPM: Budget OrigineBudget alloué 2012 Dépenses engagées 2012 Demande 2013 Fonctionnement et petits équipements IN2P Personnel, missions, fonctionnement, ANR ANR Vitesse Jan-Dec Jan-Avr 2013 Frédéric Bompard via LAL MPW run Sous-traitance et matières IN2P Mécanique/Cooling 8900 Electronique Elec+mécanique CERN 9000 Ti tube Octobre HV2FEI4-2 Novembre 4000 Carte PCB-HV Octobre 3000 Soudure Ti Oct-Dec 2000 Sonar (CO2) Oct-Dec

18 Phase0 en 2013 Assemblage/test IBL6000 Fonctionnement Pixel+IBL4000 Upgrade sonar (thermosiphon, FPGA, CO2)2500 Total12500 Paris-LPNHE ATLAS pixel18

19 Mechanique/cooling PhaseI-II en 2013 Proto tubes 7000 Assemblage staves IVW19000 Test thermique CO Total30000 Paris-LPNHE ATLAS pixel19

20 RD electronique PhaseI-II en 2013 FE-I4-B Interface USBpix3000 Chip test FE-I4-C 2x2mm 130nm14000 PCB FE-I4-C4000 PC banc de test FE-I41500 HVCMOS run AMS 180nm15000 HVCMOS run GF 130 nm15000 Flip-chip tests HV2FEI45000 PCB et DAQ HVCMOS2000 PC HVCMOS1500 Run 65 nm20000 Licence Cliosoft2000 PCB 65nm2000 Total85000 Paris-LPNHE ATLAS pixel20

21 Paris-LPNHE ATLAS pixel21 Conclusions Faits marquants Grand succès de FE-I4-A/B – le plus grand chip hybride HEP au monde Excellente qualité du tier analogique aminci à 10 µm, cross talks entre deux tiers en électronique 3D Communication entre tier analogique et digital FE-TC4- P1 (tous les pixels connectés) IBL sur le planning accéléré de 2 ans HV2FEI4 fonctionnel et communique avec FE-I4 HV2FEI4 détecte des particules sur la sortie ampli même après 375 MRads

22 Spare Paris-LPNHE ATLAS pixel22

23 Last qualifications steps The final stave design have been thermally qualified and is under Thermal and pressure cycles Stave TFOM is bellow 17°C cm 2 /W which is acceptable and within expected values Power up to 345W on a stave and system permit to maintain the sensor to -15°C which is a good input to prevent thermal runaway 23Paris-LPNHE ATLAS pixel

24 Chip électronique FE-I4 FE-I4 conçu pour l'IBL pour grands taux d'occupation et de résistance aux radiations –Pixels de 250 * 50 µm –Techno IBM 130 nm, testée jusqu'à 400 MRads FE-I4-A – record de taille HEP: 80 columns×336 rows = pixels/FE, 20x19 mm, 87 M transistors FE-I4-B -- retour décembre 2011, premiers tests très positifs- Contributions design ASIC CPPM: – Registres de configuration (local et global) – Discriminateur basse consommation – Capteur de température – ADC (lecture alims, courant de fuite, température etc) – Multiplexeur analogique – Buffers de lecture des signaux analogiques – Générateur de calibration – Amplificateur opérationnel multi-usage Paris-LPNHE ATLAS pixel24 Cooperation IN2P3: Daniel Dzahini (Grenoble) Renaud Gaglione (Annecy ) Julien Fleury (LAL) CPPM

25 FE électronique FE-I4 Caractérisation et test SEU des registres avec le faisceau de protons PS CERN protons/spill Paris-LPNHE ATLAS pixel25 Mémoire SEU CPPM CPPM

26 Test of first 3D wafers Two wafers de 3D assemblies arrived CPPM September Third wafer was diced into chips. Problems with uniformity of the thinning of the upper tier: 15-20% of the wafer surface is defective. Measurements of the resistance of daisy chains and power pads have shown the short circuits between copper surface contacts between two tiers. Few chips without shorts selected. They works, but no communication between tiers established. Problem identified by Tezzaron to be bad wafer alignment at new production facility at Tempe(AZ). The same alignment problem probably creates weak adhesion and non-uniformities during thinning. Next batch of wafers will bonds at facility at Austria in November 2011 with final delivery in spring Paris-LPNHE ATLAS pixel

27 Performance of analog tier from 3D wafer with 10 µm thickness Excellent performance of the analog tier with 10 µm thickness. 27Paris-LPNHE ATLAS pixel

28 28 FE-TC4-DS simple digital tier Digital input (test) or Tier1 output Read-out shift register (1b) 11 DRUM cells (noise generator) DRUM cell structure: 5 columns without any shielding (reference), 4 columns with shielding in metal 5, 2 columns with shielding in metal 3, 2 columns with both shielding. Tested at CPPM lab Test Shielding strategy : Paris-LPNHE ATLAS pixel

29 Mapping of threshold no DRUM activated Mapping of noise no DRUM activated Mapping of threshold with DRUM activated Mapping of noise with DRUM activated DRUM ACTIVATED No DRUM ACTIVATED Noise and threshold maps after DRUM activated 29Paris-LPNHE ATLAS pixel

30 30 CPPM: Management Plan de management: Organigramme projet labo –Responsabilités CPPM ATLAS Pixel Upgrade Mécanique-Refroidissement Electronique Stave IBL ITK support Sonar Cooling FE-I4 3D 65 nm HV–HR CMOS A-B C C GF Tezzaron AMS 180nm GF 130nm vialast


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