Presentation on theme: "RF Power improvement of AlGaN/GaN based HFETs and MOSHFETs"— Presentation transcript:
1 RF Power improvement of AlGaN/GaN based HFETs and MOSHFETs Fox, M. MarsoCWRF2008 CERN1 I will show a few steps to improv the power performans of AlGaN/GaN based HFETs and MOSHFETs by means of rf characterization and device modelling
2 Research Center Juelich? Where:between Cologne>>>>>Aachenareas of research :M aterialE nvironmentI nformationL ifeE nergieEstablished more than 50 years2 First let ma indroduce our Research Center
3 simulated and measured OutlineintroductionMeasurementssimulated and measuredRF-power performanceComparison ofConclusionS-ParameterRF-powerLoad-PullRF-power SimulationModellingDC-, S-parameteranalysisLoad-PullSimulation3the outline of my talk is given by this structureAfter a short introductionStarts with mesurements for sparameter and for rf power by means of the loadpull system.Steps for Rf power simulation are: modeling, dc- and s-parameter analysis and load-pull simulation..to verify the measured results
4 Application example4 due to Material properties wich i will show later AlGaN Material is a good candidate for high power and high temperature applicationsAlGaN based HFETs are used in Amplifier systems ...as shown here .... for example in wireless base stations as power Transistor in the output- amplifier stage.EfficiencyAlGaN/GaN HFETs are used in rf-generators, telecommunication and other applications where power devices at higher frequencies, voltages and temperatures are needed.
5 AlGaN/GaN Heterostructure and 2DEG OhmiccontactGSchottkycontactDOhmiccontactheterostructure is the layer system with different band gap material e.g. with AlGaN grown on GaN.This 2DEG “charge plate” creates the area with very high mobility and sheet concentration of carriersthe Heterostructure is formed by 2 layers with different band gap energie e.g. AlGaN is grown on GaNa 2 DEG will be established. It acts like a chrge plate and creates the area with high mobility and high sheet carrier concentration. Source and drain are ohmic contcts and will be controlled by the Schottky Gate. We allso call this Transistor HEMT.High Electron Mobility TransistorOhmic contacts are controlled by the Schottky Gate conntactFormation of 2DEG in AlGaN/GaN heterostructure
6 How to improve power performance Example I-V characteristicImaxMax. output power: f(Ids,Vds)Pout= Imax* (Vbreakdown-Vknee ) /8ClassA operating pointImax increases due to increase carrier density and velocityVbreakdown increases e.g.-with fieldplate technology-wide bandgapVkneeVbreakdown6 The maximum Outputpower obtainable by a device in Class A operation with full gate modulation is defined by I-V charachteristic of Ids,UdsThe maximum output Voltage and current swings give output power for a sinusoidal input of: Pout= (Imax* Vbreakdown-Vsaturation) /8Imax is the value of Ids corresponding to a forward gate bias. The optimum Load resistance : RL= (Vb-Vs)/Imax Large values of Imax obtained by placing in parallel a number of hemt cells to give a large total gate width. The number of gats put in parallel is limited by the minimum load resistance which can be presented by the device RL The breakdown voltage is determined principally by the avalanche breakdown of the gate to drain diode. This are related by the equationOpt. RL=(Vb-Vs)/Imaxfor increasing Pout an output voltage- and current increase is needed
7 Theory of HFETs: DC behavior How do the DC measures translate into device geometry and material properties?Drain Current (Ids)Transconductance (gm)absolute charge underneath the gate equals charge in active region of 2DEG:hWLGqn0rIdinsertion of expression into saturated current formula......yields:7 i`l give a few hints of the DC behavior from the IV characteristicUp to the suturation the current is depending from carier concentration, mobility, W and e-fielde_: q=1,602x10^-19C [As]N= number of electronsMobilityVds/dds= elektr fieldVs=saturation velocityVddifferentiation yields intrinsic transconductancethe formulas tell us to:charge carrier concentration mobility, velocity (robertson2001a)
8 Advanced Material Properties Important for high output power:- high breakdown field and voltage, i.e. wide bandgaphigh thermal conductivityImportant for high fT and fmax :Fast carriers (i.e. µ0, vpeak , vsat)Frank Schwierz Fachgebiet Festkörperelektronik, Technische Universität Ilmenau, Germany1.22.90.050.51.3k, W/cm-K1.5-220.70.81vsat, 107cm/s2.52.5-3vpeak, 107cm/s68034061070004700710m0, cm2/Vs40303346.45.7EBR, 105 V/cm3.4220.127.116.11EG, eVGaN6H SiC4H SiCInGaAs*GaAsSi8 Show a comparition of the material properties of the interested MaterialsFor high Ud: EG: band gap energie Ebr Breakdown voltageFor Id: Mobility Peakvelocety saturation velocityEven mobility is´nt high the performance of GaN based devices gives the best resultssince n is 10x higherheat transport: Temperatur coefficientessential for power devices
9 HFET performance improvement degradation of dc andtransport properties due tolong S_D distance*Juraj Bernat „Fabrication and characterisation of AlGaN HEMT“ (Diss Aachen)9 how to improve the performanceTo increase the Output voltage one could enlarge the S-D distance but tis is limited due to change of the field distribution between Gate and Drain and yields in dc degradationEnlarging of the Source - Drain distance is limited
10 HFET performance improvement Fieldplate technology: Known since 1969 on Si Higher breakdown voltage Different electric field distribution between Gate and Drain*Juraj Bernat „Fabrication and characterisation of AlGaN HEMT“ (Diss Aachen)10 Implement the fieldplate technologie Is known since 1969 on Si. This will give a higher breakdown Voltage and an better field distribution between Gate and Drain.Performance improved by Fieldplate technology on AlGaN-HEMT
11 Fieldplate Technology - Results Simulation: by ATLAS, SilvacoConfirmed by: A. Koudymov, IEEE Electr. Device L. 26, Oct. 200511 Field simulations are done with a sim Program ATLAS from Silvaco.the simulation Results shown in the diagramm of electric field via the source drain distanceWith field plate implementation reduced elektric field peaks are shown.Increase of breakdown voltage in undoped structures. Breakdown of the doped structure was not changed what implies that breakdown is caused by doped AlGaN layer. Increase of the output power is due to modification of the electric field on the GaN cap surface and therefore reduction of CC.*Juraj Bernat „Fabrication and characterisation of AlGaN HEMT“ (Diss Aachen)Increase of the output power is due to modification of the electric field on GaN cap
12 ExperimentSimultaneous fabrication of unpassivated & passivated SiC/GaN/AlGaN HFETs and MOSHFETs:10 nm SiO2 layer for passivated HFETs and MOSHFETs (PECVD),LG= µm, LW =200 µm (2-fingers),Gero Heidelberger:Technology related issues regarding fabricationSiO2 ~10 nmSiO2 ~10 nmSourceDrainGateSDG30 nm Al0.28Ga0.72N3 µm GaN13 Intreducing the experiment the different HEMT structorsour AlGaN HFET structure were prepared by low pressure mettallorganic chemical vapordeposition on SiC and standard device processing. …as shown here with S G D metallization For the HFET.Passivation is done by plasma enhanced chemical vapor deposition with silicon oxide thickness of 10nmAdditionaly dielectric layer underneath the Gate coming to Metall-oxide-semiconductor-hetero field-effect-transistor with 10nm oxide thickness deposited by PECVD prozessLG ….Gate with4H-SiCUnpassiv. HFETpassivatedHFETMOSHFET
13 Fabrication of our HFET Devices HFET- technologyMesa etchingECR RIE or Ar+ sputterDepth: 250 ~ 300 nmOhmic contactsTi/Al/Ni/AuAnnealing: 850ºC, 30secSchottky contactsNi/AuPadsTi/Au12 Our Hemt technologie are demonstrated here:Mesa etching to isilate the HEMT cell from the other ciruits on the WaferOhmic conntacts for Source and Drain Contacts,The Pads to make the On wafer measurements with the apropreate Probe tips.Passivation process with Plasma enhanced chemical vapor deposition.Fabrication of our HFET Devices
14 Hetero Field Effect Transistor HFET LayoutSEM picture of AlGaN/GaN HFET wg=200 µmLg=0.3 µmSEM picture of AlGaN/GaN HFET with airbridge technology >> increasing Imax14 This pictures show thw princible of our HEMT layoutThe upper draw is a scanning electron microscop picture of a single HEMT CellWith Source gate and drain metallazation. Source is grounded, Gate is Input, Drain will be output.The double Gate is with is 2x100micrometer and the gatelength is 0.3 micro.Thelower draw is a scanning electron microscop pcture of multible HEMT in parallel connected with airbridges.This will increase the maximum output current wich i will show later on.Detailed view of HFET Device as fabricated in our labprepared for on-wafer measurements with 100 µm pitch
15 simulated and measured OutlineMeasurementssimulated and measuredRF-power performanceComparison ofS-ParameterRF-powerLoad-PullRF-power SimulationModellingDC-, S-parameteranalysisLoad-PullSimulation15 Sparameter measurement
16 S-parameter Measurement System Important for microwave design and characterizationBasics for parameter extraction and simulationOur measurement system:Frequency up to 110 GHzNetwork AnalyzerOn wafer measurementsControl System and Calibration (LRM)16 Next Slide and the Photogragh will show oure Measurement Setup for S- Parameter Measurementss parameter measurements are important parameters in an microwave design.Travelling waves are scattered or reflected at the terminal from the DUTSparameter measurements are performed with networkanalyzer up to 110 GHz on wafer measuremnt system.
17 110 GHz Measurement System HP8510XF NWA-System:-Network Analyser HP8510C- RF source 45 MHz 50GHzSynth. sweeper HP 83651-LO source 45MHz to 20GHzSynth. Sweeper HP 83621-mm-wave controller-Cascade probestation-Connectors: 1 mm coaxial-Coplanar Probetips 110 GHz-LRM Calibration , attanuationDUTmm-wave controllermm-wave controller17 The 110 Ghz Measurement system consists of: network analyzer Agilent HP 8510 C ,Bias supply, Probe station for On-wafer Measurements , Coplanar probetips, Mixer, Controller and Directinalcoupler are situated on the 3Dimensionel Tabel next to the DUT to avoid rf loses.FZ-Jülich, ISG1, A. FoxWe are well prepared for high quality s-parameter measurements
18 Results of S-parameter measurements drain source voltage: 20Vgate length: nmSiO2 layer thickness: 10nmcut off frequency (ft) is the frequency where current gain h21=0 [db]18 measurement results presented in diagramm with current gain H21 vs. FrequencyDrain source voltage 20V lg 500nm sio2 layer 10nmThe cutoff frequency is determined as zero gain value of current gain H21For the Hfet we found cutoff frequency of 17 Ghz for MOSHFET increase to 24 GHz.MOSHFETs show significantly higher cut off frequencies
19 Variation of ft vs. gate length 9 The cutoff frequency decreases for all types of devices with increasing gate length, as shown.Higher cut-off frequencies (ft) are observed for MOSHFETs for all kinds of gate lengths. ft increases with decreasing gate lengths.
20 simulated and measured OutlineMeasurementssimulated and measuredRF-power performanceComparison ofS-ParameterRF-powerLoad-PullRF-power SimulationModellingDC-, S-parameteranalysisLoad-PullSimulation20 Load pull mesurements
21 Load Pull Measurement System RF-Power measurementstep attenuatorMicrowave Tuner Systemslotted coaxial linecomputer controlled slug Tuner cal.deembedingFocus MicrowaveRef.planeresonanz.21 The Load pull measurement system consist of probestation to handle the probe for on wafer measurements. The input power is generated...Load Pull Measurement System
22 RF-Power measurement system NetworkanalyzerHP8510BBias supplySource-tunerLoad-tunerDUT22 The picture shows our rf- power load pull mesurement system with network anlyzer ...in the rear for... calibration and deembeding.The large signal measurements were performed on wafer... at 7 GHz.... under continuous wave condition ....using the Focus Microwave computer controlled tuners.... with mechanical airline..... and computer controlled stubs.All measurements were made at room temperature.The source and load reflections GS and GL were optimized .....for maximum output power.Large signal measurements are performed with a load- and source- pull measurement system to match input and output impedances of the device to achieve maximum output power.The input-side tuner allows the source match to be "pulled" to an impedance where the device has appreciable gain, then it is generally left at this fixed impedance for all measurements on a device at a fixed frequency. The output-side tuner is the one that gets a work-out!FZ-Jülich, ISG1, A. FoxLarge signal measurements were performed on wafer at 7 GHz by source and load pull measurements
23 Load pull measurement23 Measurement results Pout, Gain and PAE for passivated HFET with differend OutputvoltagePower performance will increase with further increase of Vdsfor passivated HFET
24 Power measurement at differend SiO2layer Comparison of Pout for HFET and MOSHFET with different SiO2 dielectric layer@ 7 GHz24 Fig shows the comparison of output power for HFET and MOSHFET with different dielectric layer thicknesses vs. input power.measured at 7 GHz. The maximum output power is found with a dielectric thickness of 5 nm.Performance improvement by optimising the dielectric layer thickness
25 Comparison of Power measurements SiO2 layer thickness: 10nmWG = 200 µm , LG = 0.7 µmf = 7 GHzVg = -2.5 V HFETVg = -2.5 V passiv. HFETVg = -7 V MOSHFET25 The results of the Loadpull rf power mesurements are shown in RF output-power vs. Output-voltage.Due to different Threshold voltage the best power out put results for MOSHFET was achieved with –7 V Inpputvoltage.The RF output power increases from 2.9 W/mm (HFET) to6.7 W/mm (MOSHFET) with no fieldplate implemented
26 simulated and measured OutlineMeasurementssimulated and measuredRF-power performanceComparison ofS-ParameterRF-powerLoad-PullRF-power SimulationModellingDC-, S-parameteranalysisLoad-PullSimulation26 Modelling was done .....to investigate the intrinsic behavior of the device structureModelling allso generats the Simulation file wich is needed for power simulation
27 Equivalent circuit for the AlGaN/GaN MOSHFET ModellingEquivalent circuit for the AlGaN/GaN MOSHFETGDSOxydedeplition27 The physical structure shown here with source gate drain contact, the deplation layer and substrate and the dielectric layer underneath the gate. From this physical- structure one comes to the equivalent circuit with its extrinsic and intrinsic behavior.Extrinsic parameters are independent from Working point. From cold measurements we get the extrinsic parameters We use this model to extract the extrinsic and intrinsic parameters from measured s-parameter by means of the extraction software Topas.The Gate source capacitance, transconductance showed an significant change with dielectric layer underneath the gate as for the MOSHFET structure.ft =f( gm/Cgs)SCgs and gm change with the dielectric layer
28 Extracted Parameters Cgs, gm 28 fig shows the input capacitance Cgs of the three devices, while the extracted high frequency transconductance is depicted in Fig.Since the dielectric layer at the gate builds a additional series capacity the gate source capacitance is decreased compared to the HFET structure. Transconductance is also decreased at the MOSHFET.With passivation the polarisation induced charge on the surface is reduced so that vsat is higher and so the gm increasesFrom theory:vsat increases with passivationCgs decreases for MOSHFETs due to additional SiO2 layer
29 Comparison of gm/Cgs ratio ModellingComparison of gm/Cgs ratioft =f( gm/Cgs)29 The cutoff frequency relevant ratio gm to Cgs vs. the drain voltage is shownThe calculated values of ft from the ratio gm/Cgs are in agreement with the increase of cutoff frequency for the MOSHFET compared to unpassivated and passivated HFET from h21gm/Cgs is in agreement with the increase of cut off frequency from h21 for the MOSHFET compared to HFET
30 Comparison of measurements and model ModellingComparison of measurements and modelS21S11MOSHFETVg=-1VVds=19VFrequency: 2 to 50GHzS12S22Measurement: blue curvesModel: red curves30 Extracted modell is verified by comparing the optimized and the measured Scattering -parameter.A good agreement has been achieved as seen here in the charts of the 4 SparametersParameterextraction done by TOPAS, IMSTGood agreement between measurement and optimized model
31 simulated and measured OutlineMeasurementssimulated and measuredRF-power performanceComparison ofS-ParameterRF-powerLoad-PullRF-power SimulationModellingDC-, S-parameteranalysisLoad-PullSimulation31By means of ADS Advanced Design System (Agilent) the analysis of dc and sparameters are done to verify the calculated parameters for further simulations.
32 DC analysis DC design circuit DC simulator bias sweep DUT DUT with the modeled parametersDUT32 Design circuit diagramm for Dc analysis is shown.DUT includes all the extracted parameter from modelling.The bias voltages for in- and output is sweeped over the desired range.Dc simulator calculats the DC values shown in next slide:Advanced Design System,Agilent
33 DC analysis: ResultsTransconductanceOutput I-V- curvesTransfer I-V- curves33 Output I-V- curvesTransfer I-V- curvesTransconductance are in good agreement to the measured DC resultsThe curves are comparable to DC-measurements and reflect the intrinsic behavior
34 S-parameter analysis S-parameter simulator S-parameter design circuit frequency sweepS-parameter design circuitDUT34 Ciruit diagramm for S parameter shownincludes the Input output Ports and Bias SuppliesDUT with the intrinsic and extrinsic parametersDesired Frequency range is sweepedS-parameter simulator calculates the Impeadances shown in next slide
35 S-parameter analysis Comparison of Transistor Scattering Parameters Input S11 output S22tranmited impeadance S21Show a good agreementmeasured: red curvessimulated: blue curvesdifferent fitting at dif. biaspointsneeds further optimazation@that working point
36 simulated and measured OutlineMeasurementssimulated and measuredRF-power performanceComparison ofS-ParameterRF-powerLoad-PullRF-power SimulationModellingDC-, S-parameteranalysisLoad-PullSimulation36 Load pull simulationLike the load pull measurement, the rf- power simulation first need a good impeadance match at in an output of the device.A pair of tuners are used. The input-side tuner allows the source match to be "pulled" to an impedance where the device has appreciable gain, then it is generally left at this fixed impedance for all measurements on a device at a fixed frequency. The output-side tuner is the one that gets a work-out!
37 Biasing the device and running a simulation Load-pull simulationSpecifying and generating desired load and source reflection coefficients (impedance)Biasing the device and running a simulationCalculating desired responses (delivered power, PAE, etc.)37 Load pull Simulation with loadpull simulation specifying and generating desired load and source reflection coefficints for max Output power or for max PAE.
39 Load pull simulation39 Output Impeadance pattern shows best match for Poeut and for PAEThis data shows the simulation results when the reflectioncoefficient is the value selected by the marker’s location.…to find the optimal value to maximize power or PAE, etc.
40 Load pull simulationHarmonic Balance simulator Input power sweepMatchedInput impedanceMatchedOutput impedanceDUT40 Loadpull simulation circuit with Harmaonic balance simulator for non linear circuit simulations.One tone sin wave generator and bias supply.Sweep of Power input.Results Pout and PAE to Compare with our Load pull measurementsNon linear circuit simulation results in Pout and PAE of the DUT
41 simulated and measured OutlineMeasurementssimulated and measuredRF-power performanceComparison ofS-ParameterRF-powerLoad-PullRF-power SimulationModellingDC-, S-parameteranalysisLoad-PullSimulation41 Verification of the measured and simulated result by comparision of simulated and measured rf power performance
42 Comparison of simulated and measured PAE MOSHFET,SiO2 thickness: 10nm42 comparing simulation and measurements of PAE.The PAE shows slight deviations since it depends on input matching.Curves are acceptable between measurement and simulation of PAE
43 Comparison of simulated and measured output power MOSHFET,SiO2 thickness: 10nm43 comparing simulation and measurements of output power of the MOSHFET via the PinGood agreement between measurement and simulation of Pout
44 Increase of RF-performance by introduction of the MOSHFET-technology. ConclusionIncrease of RF-performance by introduction of the MOSHFET-technology.- MOS-HFET superior to unpassivated and passivated HFET regarding DC-, RF-, and power-performance.Increase of output power, PAE and cut-off frequency.Simulations verify the measured large signal results.Further work: alternative dielectric material and additional fieldplate implementation44 we reported an increase of RF- performance by introduction of the MOSHFET- technology.This is demonstrated by the increase of cutoff frequency with the small signal behaviour and the increase of rf-output power with large signal performance.The simulations are in accordance to the large signal measured results and are also confirmed by the S-parameter measurements.Further investigation will be done with different dielectric materials underneath the gate.
47 RF-Power measurement (Load-Pull ) Comparison of RF-Power performance for passivated HFET and MOSHFETHFETMOSHFET14Slides show Power measurement Results. Output power and gain vs. input power with differnt output voltage.POUT increases with the drain-source voltage Vds.As can be seen, maximum of Power Addet Efficiency is not at the highest outputvoltage as the max output powerIn this case the measurements are optimised at max Poweroutput.PAE=(Pout-Pin)/PdcMOSHFETs show significantly higher output Power and PAE
48 Load pull simulation Load-Pull design circuit Harmonic Balance Input power sweepmatched source impedancematched loadimpedanceDUT26Loadpull simulation circuit with Harmaonic balance simulator for non linear circuit simulations.One tone sin wave generator and bias supply.Sweep of Power input.Results Pout and PAE to Compare with our Load pull measurementsNon linear circuit simulation results in Pout and PAE of the DUT
49 Load pull simulationDUTDetail circuit of Load-Pulldesign circuit
50 …to find the optimal value to maximize output-power Load pull simulationLoad pull simulation varies the load reflection coefficient presented to a device...…to find the optimal value to maximize output-power
51 From physical structure to equivalent circuit ModelingFrom physical structure to equivalent circuit10 Modelling was done .....to investigat the intrinsic behaviour of the HEMT structure.From the physical structure the model can be deveoped as seen...The equivalent curcuit results from the physical structure.the channel capacitance is the depletion layer contribution to the total CgsBased on the well known 15 element equivalent curcuit the the intrinsic parameters were extracted by means of the extraction software Topas.The eqc parameter Gate source capacitance, transconductance and source resistance showed an significant change with doping density.Rs decreases from 4.9 Ohm for undoped to 3.9 for highly doped devices respectively.The variation of doping concentration influences the gate channel capacitance which is the depletion layer contribution to the total gate source capacitance.
53 ModelingComparision of measured and simulated S-ParameterS12S11S22
54 increased output power by increasing Id and Ud To reach maximum Pout:High IdsatHigh VbrSmall Vknee Small Rsincreased output power by increasing Id and Ud
55 Reduction of Gate Leakage Current MOSHFET using 11nm thick SiO2 gate isolation:30% increase of the drain saturation currentReduction of gate leakage current from 10-6 to A/mm*Juraj Bernat „Fabrication and characterisation of AlGaN HEMT“ (Diss Aachen)
57 SiC and GaN based Transistors Cree, Inc : Pout= 32.2 W/mm, PAE= 54,8%, Fe_doped and Field plateGaN Pout=4.1W/mm, PAE=72%
58 Heterostructure and 2DEG A heterostructure is the layer system where two semiconductors with different bandgaps Eg are grown one on the otherIn the thermodynamical equilibrium,when both semiconductors are "connected" together, the Fermi-level energy (EF ) of the Semiconductor I and Semiconductor II must be in the line what cause the discontinuity in the conductance (EC) and valence (EV ) band and the band bending. This results in the formation of the triangular quantum well where carriers are fixed in one axis and the 2DEG is formed.