1. LHCb Week 27/10/04 J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P3 1 Level 0 Decision Unit: Debugging and Monitoring Remi Cornat, Emmanuel Delage, Julien Laubser, Jacques Lecoq, Magali Magne, Pascal Perret Laboratoire de Physique Corpusculaire de Clermont-Ferrand

2. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P32 LHCb Week 27/10/04 L0DU Overview: Global architecture Decision L1 CalMuonPile-UpSpare Control Interface Trigger Definition Unit RS world computation - decision Framework L1 ECS HLT Partial Data Processing @ 40 MHz 24 words of 32 bits @ 40 MHz 704b@ 1 MHz 1024b@ 40 KHz

3. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P33 LHCb Week 27/10/04 Control FPGA Processing FPGAs HFBR-782BE BGA connector Readout Supervisor Output 16 bits @40 MHz USB Interface (Local ECS) TTC Mezzanine 12 Deserializers TLK2501 Proc/Histo RAM Test Bench RAMs Chip FTDI I2C LVDS Bus com. // Bus com. LVDS conv 12 Deserializers TLK2501 12*(16+3) L0 trigger Processor data: 24*(32 bits @ 40MHz)

4. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P34 LHCb Week 27/10/04 Debugging Three tests are provided: - Test of the optical link between the L0DU and L0 trigger processor (Calo, Muon and Pileup sytem) - Test of the link between the L0DU and the Readout Supervisor ODIN - Test of the behaviour of the L0DU: - L0DU test bench - On board test bench

5. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P35 LHCb Week 27/10/04 Optical link Logic flow for each link: 32 bits @ 40 MHz Physical flow for each link: 16 bits @ 80 MHz In order to help detection, a switch bit is introduced to distinguishe MSB from LSB part This switch bit is always received on D[0] for the reception side Reception side Emission side LHCB 2004-055

6. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P36 LHCb Week 27/10/04 Due to the physical link, 30 bits can be used for the data Consequently, the first word bits assignment proposal is obsolete and a new bit assignment must be defined The number of bits assigned for Et, Pt, address could not be decreased The solution consists in decreasing the number of bit for: - error: 2 bits => 1 Status bit - BCID: 8 bits => 7 bits, excepted for Pileup Word2 (6 bits for BCID) Proposal for the « Status bit »: The « Status bit » is asserted high when the data are containing an error Signification of the Status when asserted high: - the incoming data could be used in the computation decision - the incoming data could not be used in the computation decision. To identify this case all others bits must be asserted low. Optical link

7. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P37 LHCb Week 27/10/04 Optical link test procedure Aim of the optical link test procedure: - to check the signal integrity - to allow to identify the optical link On the receiver side: During the optical test procedure, these datas are compared to the pattern provided by a generator similar to the one used on the transmitter side Emitter Board Processing data flow Test Pattern injection Sel. Mode Bit Single Optical Fiber Data Acquisition Test Pattern Emulation L0DU Link Diagnostic (comparaison) Sync. PC ECS

8. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P38 LHCb Week 27/10/04 Optical link test procedure Static test: - allows to identify the optical link - the choice of the pattern is made through the ECS - the receiver side is informed by ECS of the expected data - both L0DU and L0 trigger processor are informed via ECS of the running mode Circular test: - a fixed pattern is sent on the data inputs but control signals are automatically toggled - the L0DU is informed by ECS of the expected data sequence - both L0DU and L0 trigger processor are informed via ECS of the running mode LHCb. 2004-0055 Ramp test: - in this mode, the pattern which is sent is raised at each time Random test: - a Linear feedback shift register is used to implement the pseudo-random test

9. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P39 LHCb Week 27/10/04 Optical link test procedure Design kit proposal: - All L0 trigger processor will have the same procedure to check the single optical link - A design kit allows to generate the four test modes - Must be give to each part of the L0 trigger processor Input/output Design kit specification: - The configuration registers are external of the Design Kit Bloc - Each L0 trigger processor can integrate the Design Kit Bloc Gtx_Clk Rst Enable Start Config[1..0] Ident[7..0] Data_out[15..0] Tx_en Tx_er - Rst: Reset bloc signal - Enable: Validation bloc signal - Start: start signal generated by ECS - Config[1..0]: test mode selection - Ident[7..0]: Optical link Identification - Gtx_Clk: Reference Clock @80Mhz - Tx_en : Transmit enable - Tx_er: Transmit error coding - Data_out[15..0]: Transmit data bus

10. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P310 LHCb Week 27/10/04 Timing waveform Design kit specification: - Must be conformed to the TLK2501 and GOL specification - Data must be valid on the rising edge of the GTX_CLK when TX_EN is asserted high and the TX_ER is asserted Low Optical link test procedure Tsu =1.5 ns and Th = 0.4 ns Fonctionning of Design kit specification: - First, the design bloc sends a specific sequence for the synchronisation of the receiver - Second, the design bloc sends the test pattern corresponding to the test configuration mode TLK2501 Transmit Timing Waveform

11. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P311 LHCb Week 27/10/04 Readout Supervisor test procedure Aim of the Readout Supervisor test procedure: - to check signal integrity Four test modes are proposed: - a static test in which a fixed pattern is sent - a circular test - a ramp test in which the sending pattern is raised at each sequence - a random test On the Readout Supervisor side: During test procedure, these datas are compared to the pattern provided by a generator similar to the one used on the transmitter side

12. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P312 LHCb Week 27/10/04 L0DU Test Bench Overview Mother Board L0DU Prototype PGI BOARD Ethernet link VME Rack Memory boards TTC System: TTCvi,TTCvx USB Interface (local ECS) Optical Fiber VME Bus Control Ethernet cables with LVDS levels PC running on LINUX C++ for acquisition program Software requirements: - configure (L0DU, PGI, TTC,…), monitore (L0DU) - make the data acquisition - diagnostic the behaviour of the L0DU mezzanine Optical fiber ribon

13. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P313 LHCb Week 27/10/04 Debugging Test of the behaviour of the L0DU: Offline Debugging An on board test bench is implemented composed by: - RAMs, in which known stimulus are saved, programmed by ECS - RAMs, in which reponses are saved, read by ECS - A FPGA for the control of the test bench, controled by ECS Memories description (of the prototype): - Memory type: Static - Organisation: 65536 words of 16 bits - 12 ns address acces time => allows to function at 80 MHz The software of the L0DU emulates the behaviour of the L0DU and save the expected results Through ECS, the reponses are read and compared to the expected results to diagnostic the behaviour of the L0DU

14. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P314 LHCb Week 27/10/04 Test Bench Principle: - Load and send patterns stimulus - Save patterns results - compare the pattern results and the expected results - Diagnostic the behaviour of L0DU Debugging RAM Control FPGA Processing FPGA under test Pattern injection Pattern results Control Bus 16 32 20 Partial Data Processing Trigger Definition Unit Bit Sel Computation Pattern Injection Control Processing FPGA L0 Trigger Processor Datas Pattern Input Control Pattern RS computation Patterns results PC ECS

15. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P315 LHCb Week 27/10/04 Monitoring Verification of the BCID: Ensure the correct synchronisation of the different links Error Detection and Error counters Trigger counters Histogramming

16. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P316 LHCb Week 27/10/04

17. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P317 LHCb Week 27/10/04 Electronics and physical media interface (1/2): L0 Trigger Processor / L0DU The L0 trigger processors (Calo, Muon, Pileup system) data are transmitted on optical links. Electronics interface: - two optical transceivers Agilent HFBR782BE (pluggable version): 2*12 opticals signals => 2*12 low voltage differential signals - 24 Deserialisers TLK2501 from Texas Instrument: Deserialise each channel to 16 bits @ 80 MHz Physical media interface: - use of a patch pannel to connect the optical links coming from the L0 trigger processor - the front panel receives 12 single optical fiber terminated with SC connector - the rear panel is connected to a ribbon of 12 fibers via an MTP/female connector

18. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P318 LHCb Week 27/10/04 Electronics and physical media interface (1/2): Readout Supervisor ODIN / L0DU Electronics : - trigger world transmitted over a point to point 16 bits LVDS at 40MHz Physical media interface: - 3M pak connector, 34 pin (3M 3414-6600 or 6634) - ribbon cable: twisted pair flat 34C 1.27 mm

19. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P319 LHCb Week 27/10/04 Specification of the L0 Trigger Processor-L0DU Interface: Operational mode (1/4) The specification follows the specification of the ODE-Muon trigger interface: - Frame format - Word data format - Time alignment between different links - Synchronisation and Initialization Related documents: - LHCB note 2004-012, « Synchronisation of optical links using the GOL with the TLK2501 or StratixGX buffer » - LHCb note 2004-055, « Detailed Specification of the ODE-Muon Trigger interface » - LHCb note 2003-008, « High Speed ribbon optical link for the level0 muon trigger » - Datasheet Texas Instrument, « TLK2501 1.5 to 2.5 GBPS Transceiver »

20. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P320 LHCb Week 27/10/04 Specification of the L0 Trigger Processor-L0DU Interface: Operational mode (2/4) Two signals control the transmission on the emission side: TX_en and TX_er Required Control signal configuration: The frame format follows the cycle machine and contains 3654 data words The first word of the frame is programmable through ECS Before the end of the frame a programmable number of IDLE word is inserted to reinitialize the receiver side LHCB 2004-055

21. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P321 LHCb Week 27/10/04 Specification of the L0 Trigger Processor-L0DU Interface: Operational mode (3/4) Logic flow for each link: 32 bits @ 40 MHz Physical flow for each link: 16 bits @ 80 MHz In order to help detection, a switch bit is introduced to distinguishe MSB from LSB part This switch bit is always received on D[0] for the reception side Reception side Emission side LHCB 2004-055

22. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P322 LHCb Week 27/10/04 L0 Calorimeter word bits assignment LSB word Calo1514131211109876543210 Switch bit BCID[0] BCID[6..2] Adrr[0] Et[7..0] MSB word Calo1514131211109876543210 Switch bit BCID[1] Addr[13..1] LSB word Calo1514131211109876543210 Switch bit BCID[0] BCID[6..2] ‘’0’’ Total Et or SPD Mult. [7..0] MSB word Calo1514131211109876543210 Switch bit BCID[0] Status bit ‘’00000’’ Total Et or SPD Mult. [15..8]

23. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P323 LHCb Week 27/10/04 L0 Muon word bits assignment LSB word Muon1514131211109876543210 Switch bit BCID[0] BCID[6..2] Adrr[0] Pt[7..0] MSB word Muon1514131211109876543210 Switch bit BCID[1] Addr[11..1] Status bit ‘’00’’

24. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P324 LHCb Week 27/10/04 Pileup word1 bits assignment LSB word1 Pileup1514131211109876543210 Switch bit BCID[0] BCID[6..2] More Peak info[3..0] ‘’00’’ Peak position1[2..0] MSB word1 Pilup1514131211109876543210 Switch bit BCID[1] Addr[11..1] Status bit ‘’00’’

25. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P325 LHCb Week 27/10/04 Pileup word2 bits assignment LSB word2 Pileup1514131211109876543210 Switch bit BCID[0] BCID[4..2] #Hit[7..0] Peak position2 [2..0] MSB word2 Pilup1514131211109876543210 Switch bit BCID[1] Content2 [7..0] Status bit Peak position2 [7..3]

26. J.LAUBSER laubser@clermont.in2P3.fr L.P.C/IN2P326 LHCb Week 27/10/04 I/O Specification Need to validate the word assignement proposal: - position - number of bit Finalize the « Specification of the L0DU trigger input and output » LHCB note.