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Single-cycle CPU Control
Chapter 5b: Single-cycle CPU Control
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What do we need to control?
Mux - are we branching or not? Registers- Should we write data? 4 Result 1 Mux - Result from ALU or Memory? Result Sh. Left 2 Add Add Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Read address Data Memory PC Read address Zero Read data 1 Instruction [31-0] Result Write address Instruction Memory Write data 1 16 sign extend Mux - Where does 2nd ALU operand come from? 32 Memory- Read/Write/neither? ALU - What is the Operation? Almost all of the information we need is in the instruction! 5.3
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Instructions – Opcode and Function Code
R-Type Opcode RS RT RD ShAmt Function I-Type Opcode RS RT Immediate Data J-Type Opcode Immediate Data Main instruction info is in the Opcode, which can be used to set up the datapath and the primary ALU (for I- and J-types) For R-type instructions, the Function Code determines the function of the primary ALU (add, sub, mul, div, slt, and, or, etc.) 5.3
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Decoding the Instruction - Data
The instruction holds the key to all of the data signals R-type Opcode RS RT RD ShAmt Function 31-26 25-21 20-16 15-11 10-6 5-0 To ctrl logic Read reg. A Read reg. B Write reg. Not Used To ALU Control Memory, Branch Opcode RS RT Immediate Data 31-26 25-21 20-16 15-0 To ctrl logic Read reg. A Write reg./ Read reg. B Memory address or Branch Offset One problem - Write register number must come from two different places. 5.3
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We can decode the data simply by dividing up the instruction bus
Instruction Decoding Opcode: [31-26] 4 Result 1 Result Sh. Left 2 Add Add Op:[31-26] Ctrl Rs:[25-21] Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Read address Rt:[20-16] Data Memory PC Read address Zero Read data 1 Instruction [31-0] 1 Result Write address Instruction Memory Rd: [15-11] Write data 1 Read Reg A: Rs Imm: [15-0] 16 32 Read Reg B: Rt sign extend Write Reg: Either Rd or Rt Immediate Data: [15-0] 5.3
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Control Signals 5.3 Ctrl 4 1:LW,R-type 0:SW,Branch 1: Branch taken
4 1:LW,R-type 0:SW,Branch Result 1 1: Branch taken 0:Others Result Sh. Left 2 Add PCSrc Add Op:[31-26] Ctrl 1:SW 0:others 1:LW 0:others RegWrite MemWrite MemToReg Rs:[25-21] Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A ALUSrc Read address Rt:[20-16] Data Memory 1: Memory 0: R-type,Branch PC Read address 1 Zero Read data 1 Instruction [31-0] Result Write address Instruction Memory Rd: [15-11] Write data 1 RegDest 1:R-type 0:I-type Imm: [15-0] 16 sign extend 32 MemRead ? 1: LW 0: Others 5.3
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The Primary ALU The Primary ALU is right in the middle of everything... It must: Add, Subtract, And, Or, etc. for R-types (from FC) Subtract for a BEQ (from Opcode) Add to determine address for a LW, SW (from Opcode) A B Zero Result OverFlow Operation Cout Function Operation Result And 000 R = A • B Or 010 R = A Ú B Add 100 R = A + B Subtract 101 R = A - B SLT 111 R = 1 if A < B 0 if A ³ B 5.3
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Setting the ALU controls
Main Control Logic generates ALUOp signal 00: ALU adds 01: ALU subtracts 10: ALU looks at F.C. 11: Unused The instruction Opcode and Function give us the info we need For R-type instructions, Opcode is zero, function code determines ALU controls For I,J-type instructions, Opcode determines ALU controls Instruction Opcode ALUOp Funct. Code ALU action ALU control add add 100 sub subtract 101 and and 000 or or 010 SLT SLT 111 load word xxxxxx add 100 store word xxxxxx add 100 branch equal xxxxxx subtract 101 5.3
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ALU Control Signals 5.3 ALU Control - A function of: ALUOp
4 Result 1 Result Sh. Left 2 Add PCSrc Add Op:[31-26] Ctrl RegWrite MemWrite ALUSrc MemToReg Rs:[25-21] Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Read address Rt:[20-16] Data Memory PC Read address 1 Zero Read data 1 Instruction [31-0] Result Write address Instruction Memory Rd: [15-11] Write data 1 RegDest Imm: [15-0] 16 32 ALU Ctrl 00: Add 01: Sub 10: R-type sign extend MemRead FC:[5-0] 6 ALUOp ALU Control - A function of: ALUOp and the function code 5.3
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Inside the control oval
00:Mem 01:Branch 10:R-type 0:Reg 1:Imm 1:Mem 0:ALU 0:Rt 1:Rd 1:Branch Reg ALU Mem Reg Mem Mem Instruction Opcode Write Src To Reg Dest Read Write PCSrc ALUOp R-format LW SW x x BEQ x x This control logic can be decoded in several ways: Random logic, PLA, PAL Just build hardware that looks for the 4 opcodes For each opcode, assert the appropriate signals Note: BEQ must also check the zero output of the ALU... 5.3
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Control Signals 5.3 We must AND BEQ and Zero Ctrl 4 Add Add
4 Result 1 Result Sh. Left 2 Add Add PCSrc BEQ Ctrl MemToReg MemRead Op:[31-26] MemWrite ALUOp ALUSrc RegWrite RegDest Rs:[25-21] Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Write Read Read address Rt:[20-16] Data Memory PC Read address 1 Zero Read data 1 Instruction [31-0] Result Write address Instruction Memory Rd: [15-11] Write data 1 Imm: [15-0] 16 ALU Ctrl sign extend 32 FC:[5-0] 6 5.3
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Jumping 5.3 Ctrl 4 Add Add Data Memory Registers Instruction Memory
32 1 Sh. Left 2 Concat. 26 28 4 4 Result 1 [31-28] Result Sh. Left 2 Add Add Jump PCSrc J:[25-0] BEQ Ctrl MemToReg MemRead Op:[31-26] MemWrite ALUOp ALUSrc RegWrite RegDest Rs:[25-21] Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Write Read Read address Rt:[20-16] Data Memory PC Read address 1 Zero Read data 1 Instruction [31-0] Result Write address Instruction Memory Rd: [15-11] Write data 1 Imm: [15-0] 16 ALU Ctrl sign extend 32 FC:[5-0] 6 5.3
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Performance What major functional units are used by different instructions? R-type: Instr. Fetch Register Read ALU Register Write 6ns LW: Instr. Fetch Register Read ALU Memory Read Register Write 8ns SW: Instr. Fetch Register Read ALU Memory Write 7ns Branch: Instr. Fetch Register Read ALU 5ns Jump: Instr. Fetch 2ns Assume the following times: Since the longest time is 8ns (LW), the cycle time must be at least 8ns. Memory Access: 2ns ALU: 2ns Registers: 1ns
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