1. ASIC Design

2. ASIC Design Flow

3. Hierarchy in DC The group and ungroup commands provide the designer with the capability of altering the partitions in DC, after the design hierarchy has already been defined by the previously written HDL code. dc_shell> current_design top dc_shell> group {U1 U2} –design_name sub1

4. Total Negative Slack The WNS is defined as the timing violation (or negative slack) of a signal traversing from one startpoint to the endpoint for a particular path.

5. Stuck-At Faults How does a chip fail? –Usually failures are shorts between two conductors or opens in a conductor –This can cause very complicated behavior A simpler model: Stuck-At –Assume all failures cause nodes to be “stuck-at” 0 or 1, i.e. shorted to GND or VDD –Not quite true, but works well in practice

6. Test Example SA1SA0 A3 {0110}{1110} A2{1010}{1110} A1{0100}{0110} A0{0110}{0111} n1{1110}{0110} n2{0110}{0100} n3{0101}{0110} Y{0110}{1110} Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}

7. Design for Test –Scan insertion –Memory BIST insertion –Logic BIST insertion –Boundary-Scan insertion

8. Scan Chain Convert each flip-flop to a scan register –Only costs one extra multiplexer Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register Contents of flops can be scanned out and new values scanned in

9. Memory BIST controller logic that uses various algorithms to generate input patterns that are used to exercise the memory elements of a design (say a RAM). The BIST logic is automatically generated, based upon the size and configuration of the memory element. It is generally in the form of synthesizable Verilog or VHDL, which is inserted in the RTL source with hookups, leading to the memory elements. Upon triggering, the BIST logic generates input patterns that are based upon predefined algorithm, to fully examine the memory elements. The output result is fed back to the BIST logic, where a comparator is used to compare what went in, against what was read out. The output of the comparator generates a pass/fail signal that signifies the authenticity of the memory elements.

10. Logic BIST A similar technique using appropriate input vectors and checking the result against a comparator

11. Design Example Design a logic BIST structure for the circuit of slide 6: –Create a ROM to feed the test vectors –Use a MUX to select between the normal input and the test vectors –Create a comparator for the output that checks for the expected values