1. New AMchip features Alberto Annovi INFN Frascati

2. Outline Use of patterns Variable size patterns New input busses Disabling patterns –Increase effective production yield Annovi, 27-09-2010 2

3. 3 The Event... The Pattern Bank Pattern matching

4. Annovi, 27-09-2010 4 1.Find low resolution track candidates called “roads”. Solve most of the pattern recognition 2.Then fit tracks inside roads. Thanks to 1 st step it is much easier Tracking with ~offline quality Super Bin (SB) Tracking in 2 steps Critical parameter: SS size Affects: - Number of patterns for given efficiency: cost - Number of found roads: workload for next step Critical parameter: SS size Affects: - Number of patterns for given efficiency: cost - Number of found roads: workload for next step

5. Pattern efficiency Annovi, 27-09-2010 5 90% # of patterns in Amchips (barrel only, 45  degress) 65M500M Pattern size r-  : 24 pixel, 20 SCT 36 pix z Pattern size r-  : 12 pixel, 10 SCT 36 pix z = 342k = 40k Want this

6. Efficiency curve Annovi, 27-09-2010 6 # of pattern in Amchips (barrel only, 45  degress) Need many patterns for little efficiency ?? Super Bins are discrete Edge effects give lots of patterns with little coverage

7. Annovi, 27-09-2010 7 TSP simulation & varying-resolution pattern banks Guido Volpi & Roberto Vitillo - Pisa Depth 0 Depth 1 Depth 2 PARENT PATTERN FAT ROAD Thin ROAD AM resolution TSP resolution We do have now a structured “pattern bank”, where each thin road is connected to its parent pattern in FTKsim. Ongoing tests for TSP algo after the RoadFinder (AMsim) in FTKsim; we have studied the bank composition and AM FAKE roads. AM Fake road is a AM matched pattern whose kids do not match the event Low probability to fire AM patterns: few kids (1 or 2): big advantage to match it at TSP resolution! All blank Half-SS can fire @ AM level as fakes while @ TSP level the fake has good probability to be deleted LOW coverage patterns High probability to fire AM patterns (symmetric): many kids (up to 20 or more): no advantage to match it at TSP resolution! More than one kid can fire @ TSP level. Low probability to be a fake AM road HIGH coverage patterns KID PATTERN @Depth 0 PARENT @Depth 1

8. Annovi, 27-09-2010 8 We can use don’t care on the least significant bit when we want to match the pattern layer @ AM resolution or use all the bits to match it @ TSP resolution Test of AM patterns: 1.all single kid patterns @ TSP resolution 2.For all few kid patterns use don’t care only for layers where both Half-SS are used by kids AM resolution (don’t care ) TSP resolution (care) to exclude the right half in these layers Guido Volpi & Roberto Vitillo - Pisa All AM roads AM roads with at least 1 matched kid Fake AM roads # of kids WH @10 34 How to implement “variable resolution” in the AMchip AM pattern distribution vs Number of kids Majority of patterns with a single Kid AM & TSP Pattern Bank for 23 ev. pileup # of kids

9. AM with care/don’t care Annovi, 27-09-2010 9 TSP38000 AM@TSP28000 AM@DC44000 AM342000 Care/don’t care very effective to reduce the number of roads. Area cost on the chip approx. 1 extra cell for each DC bit. Now 15 cells/layers. With 1 DC bit area increases by 1/15 ~ 7%. For comparison going to TSP resolution would require 3x patterns. # of kids

10. Number of busses Currently we have 6 input busses New AMchip should handle 8 layers IBL will require 2 busses for higher b/w External SCT layers needs half b/w Current package constraint max 7 input busses 3 options: implement 2 of them to be selected online Annovi, 27-09-2010 10

11. 8 Layers vs 7 buses (option 1) Annovi, 27-09-2010 11 Pattern bank with 8 matching layers 8 internal buses Internal register that feeds 8 busses Input register for 7 busses Demultiplex based on MSB E xt ra PixPix PixPix PiXPiX SCTSCT SCTSCT SCT 2 & 3

12. IBL: 7 Layers vs 7 buses Annovi, 27-09-2010 12 Internal register that feeds 8 busses IBLIBL IBLIBL PixPix PiXPiX SCTSCT SCTSCT SCT 2 & 3 Input register for 7 busses Demultiplex based on MSB IBL @ double bandwidth. Either double internal clock, or special logic. Take the logical OR of 2 layers. Both layers store the IBL super bin. Distribute 50% data to each layer. Layer matches if any of 2 IBL layers match Special IBL layer: OR of 2 layers

13. IBL: 8 Layers vs 7 buses Annovi, 27-09-2010 13 Internal register that feeds 8 busses IBLIBL IBLIBL PixPix PiXPiX ?????? SCTSCT SCT 2 & 3 Input register for 7 busses Demultiplex based on MSB IBL @ double bandwidth. Either double internal clock, or special logic. Take the logical OR of 2 layers. Both layers store the IBL super bin. Distribute 50% data to each layer. Layer matches if any of 2 IBL layers match IBL with double clock

14. Amchip 03 yields AMchip03 prototype 2004 –1cm^2 MPW yield 35% AMchip03 production 2005 –1cm^2 pilot run yield 70% Large fraction of failures due to single pattern defect. Add one register to disable bad patters –Will allow to use all chips with a single (or few) pattern defects. Area cost small :1 flip-flop/pattern (not /layer) Annovi, 27-09-2010 14

15. Changes to AMChip specifications Amchip 03 specs: –http://www- cdf.fnal.gov/publications/cdf7339_amchip0 3_specs.pshttp://www- cdf.fnal.gov/publications/cdf7339_amchip0 3_specs.ps New features –Add 1 or 2 don’t care bits/layer –Increase input busses to 7 with multiplexing & special handling of IBL –Add disable FF for each pattern Annovi, 27-09-2010 15

16. BACKUP Annovi, 27-09-2010 16

17. Annovi, 27-09-2010 17 Milestone #9: Specify system size..1×10 34 and 3×10 33 Concentrate now on 2013-2015 (17-19 pile-up events) 2020 comes much later and will profit of a very advanced technology……. Sim with 75 pile-up events after 2020! 17,6 pile-up ev. @2.6 10 33 19,0 pile-up ev. @ 10 34

18. Annovi, 27-09-2010 18 Using the variable resolution in a new AM chip for 10 34 WH events @10**34 (# of pile-up events = 23) Banks coverage ~ 95% 8.0 MPat @TSP → 2,80 MPat @ AM level (35%) per region (barrel only) 20 MPat @ TSP → 7 MPat @ AM level (35%) per region (all detector) Using TSP resolution in the AM bank for AM patterns with 1,2,3 kids: 3600 goes down to 1325 roads/AMboard → gaining a factor ~ 3! For a full detector FTK: less than 4000 roads/AMboard @AM out with a limit of 8000. less than 2000 roads/AMboard @TSP out with a limit of 4000. Guido Volpi & Roberto Vitillo - Pisa FTK Demonstrator with old chip, barrel only: running now on 17,6 pile- up events to understand DATA FLOW → however we consider it a test, It is not necessary to have large margins for 2013. Even a small AMchip (12 mm 2 ) @ 65 nm (MPW 80 k€) with variable resolution implemented, could do it, even without the TSP. Very low consumption DATA FLOW (Option A) assuming 16 AMboards in a core crate (numbers are for barrel only – a factor ~2,5 has to be applied for “all detector”): 3600 roads/AMboard of which 733 have a kid match at TSP level → 80% fakes

19. Annovi, 27-09-2010 19 180 nm 90 nm NEXT YEAR – MAY BE MARCH Mini-asic COULD be 90 or 65 nm THE AMCHIP04 PROTOTYPE Design: L.Sartori (Ferrara) M.Beretta (LNF) E. Bossini, F. Crescioli, I.Sacco (Pisa) Test: A.Lanza (Pavia) 90 nm miniasic