1. Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 21, 2012 Crosstalk

2. Today Crosstalk –How arise –Consequences –Magnitude –Avoiding Penn ESE370 Fall2012 -- DeHon 2

3. Capacitance There are capacitors everywhere Already talked about –Wires as capacitors –Capacitance between terminals on transistor Penn ESE370 Fall2012 -- DeHon 3

4. Miller Effect For an inverting gate Capacitance between input and output must swing 2 V high Or…acts as double- sized capacitor Penn ESE370 Fall2012 -- DeHon 4

5. Capacitance Everywhere Potentially a capacitor between any two conductors –On the chip –On the package –On the board All wires –Package pins –PCB traces –Cable wires –Bit lines Penn ESE370 Fall2012 -- DeHon 5

6. Capacitor Dependence Decrease with conductor separation Increase with size Depends on dielectric Penn ESE370 Fall2012 -- DeHon 6

7. Parallel Wires Parallel-plate capacitance between wires Penn ESE370 Fall2012 -- DeHon 7

8. Wire Capacitance Changes in voltage on one wire may couple through capacitance to another Penn ESE370 Fall2012 -- DeHon 8

9. Consequences Qualitative First Penn ESE370 Fall2012 -- DeHon 9

10. Driven Wire What happens to a driven wire? Penn ESE370 Fall2012 -- DeHon 10

11. Driven Wire Can this be a problem? What if victim is: –Clock line –Asynchronous control –Non-clock used in synchronous system Outputs sampled at clock edge Penn ESE370 Fall2012 -- DeHon 11

12. Undriven Wire What happens to undriven wire? Where do we have undriven wires? Penn ESE370 Fall2012 -- DeHon 12

13. Clocked Logic CMOS driven lines Clocked logic Willing to wait to settle Impact is solely on delay –May increase delay of transitions Penn ESE370 Fall2012 -- DeHon 13

14. Magnitude Quantitative Penn ESE370 Fall2012 -- DeHon 14

15. How large is the noise? V 1 transitions from 0 to V? Penn ESE370 Fall2012 -- DeHon 15

16. How large is the noise? V 1 transitions from 0 to V Penn ESE370 Fall2012 -- DeHon 16

17. Noise Magnitude Penn ESE370 Fall2012 -- DeHon 17

18. SPICE C 1 =10pF, C 2 =20pF Penn ESE370 Fall2012 -- DeHon 18

19. Good (?) Capacitance High capacitance to ground plane –Limits node swing from adjacent conductors Penn ESE370 Fall2012 -- DeHon 19

20. Driven Line What happens when victim line is driven? Penn ESE370 Fall2012 -- DeHon 20

21. Driven Line Driven line –Recovers with time constant: R 2 (C 1 +C 2 ) Penn ESE370 Fall2012 -- DeHon 21

22. Spice : R 2 =1K, C 1 =10pF, C 2 =20pF Penn ESE370 Fall2012 -- DeHon 22

23. Magnitude of Noise on Driven Line Magnitude of diversion depends on relative time constants –   <<  2 –   ~=  2 –   >>  2 Penn ESE370 Fall2012 -- DeHon 23

24. Magnitude of Noise on Driven Line Magnitude of diversion depends on relative time constants –   <<  2 full diversion, then recover –   ~=  2 –   >>  2 Charge capacitor faster than line 1 can change –little noise Penn ESE370 Fall2012 -- DeHon 24

25. Spice: C 1 =1pF, C 2 =2pF Penn ESE370 Fall2012 -- DeHon 25

26. Switching Line with Finite Drive What impact does the presence of the non switching line have on the switching line? –All previous questions were about non-switching –Show R on switching Penn ESE370 Fall2012 -- DeHon 26

27. Simultaneous Transition What happens if lines transition in opposite directions? Penn ESE370 Fall2012 -- DeHon 27

28. Simultaneous Transition What happens if transition in opposite directions? –Must charge C 1 by 2V –Or looks like 2C 1 between wires Penn ESE370 Fall2012 -- DeHon 28

29. Simulation V2 switching at ¼ frequency of V1 No crosstalk reference case where no V2 Penn ESE370 Fall2012 -- DeHon 29

30. Crosstalk Victim Simulations Penn ESE370 Fall2012 -- DeHon 30

31. Where Arise Penn ESE370 Fall2012 -- DeHon 31

32. Cables and PCB Wires Penn ESE370 Fall2012 -- DeHon 32 Source; http://en.wikipedia.org/wiki/File:Flachbandkabel.jpg

33. Printed Circuit Board Penn ESE370 Fall2012 -- DeHon 33 Source: http://en.wikipedia.org/wiki/File:Testpad.JPG

34. 34 Interconnect Cross Section ITRS 2007 Penn ESE370 Fall2012 -- DeHon 34

35. IC Metalization Penn ESE370 Fall2012 -- DeHon 35 Source: http://en.wikipedia.org/wiki/File:Silicon_chip_3d.png

36. Penn ESE370 Fall2012 -- DeHon Standard Cell Area invnand3 All cells uniform height Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die http://microscope.fsu.edu/chipshots/intel/386dxlarge.html 36

37. Wires Will be capacitively coupled to many adjacent wires of varying degrees Penn ESE370 Fall2012 -- DeHon 37

38. bit lines, word lines Penn ESE370 Fall2012 -- DeHon 38 Source: http://techon.nikkeibp.co.jp/article/HONSHI/20071219/144399/ bitline wordline

39. Addressing Penn ESE370 Fall2012 -- DeHon 39

40. What can we do? How can we reduce? Penn ESE370 Fall2012 -- DeHon 40

41. What can we do? Orthogonal routing layers –Avoid parallel coupling vertically Widen spacing between wires –Particularly critical path wires Limit length two wires run in parallel Separate with power planes Separate with ground/power wires Penn ESE370 Fall2012 -- DeHon 41

42. Idea Capacitance is everywhere Especially between adjacent wires Will get “noise” from crosstalk Clocked and driven wires –Slow down transitions Undriven wires voltage changed Can cause spurious transitions Penn ESE370 Fall2012 -- DeHon 42

43. Admin Project 3 due Thursday after break Back here Monday and Wednesday In lab on Friday Penn ESE370 Fall2012 -- DeHon 43