1. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Representative 3D integration scheme showing vertical stacking of Si chips containing copper TSVs. The schematic is not to scale, and the possible underfill material and other peripheral structures are not included. Figure Legend:

2. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Finite element model of a representative TSV/microbump bonding structure connecting two adjacent silicon chips, with an underfill layer around the joint region. The dashed line represents the path along which the stress profiles and carrier mobility changes are shown in Sec. 3.3. Figure Legend:

3. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Finite element mesh (a) without and (b) with an underfill layer. (c) Comparison of the σ zz stress profiles in Si, along the dashed line shown in Fig. 2, based on three different finite element meshes for the model without underfill. Meshes 2 and 3 are coarser than mesh 1 (used in the current model); the representative element sizes in meshes 2 and 3 are approximately 1.6 and 2.8 times, respectively, that in mesh 1. Figure Legend:

4. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of stress σ xx in the structure (a) without and (b) with the underfill Figure Legend:

5. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of stress σ yy in the structure (a) without and (b) with the underfill Figure Legend:

6. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of stress σ zz in the structure (a) without and (b) with the underfill Figure Legend:

7. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of hydrostatic stress in the structure (a) without and (b) with the underfill Figure Legend:

8. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of stress σ xy in the structure (a) without and (b) with the underfill Figure Legend:

9. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of equivalent plastic strain in the structures (a) without and (b) with the underfill Figure Legend:

10. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of (a) stress σ xx and (b) equivalent plastic strain in the structures without underfill, when the solder alloy is replaced by the intermetallic Figure Legend:

11. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of stresses (a) σ xx, (b) σ yy, (c) σ zz, (d) σ xy, and (e) equivalent plastic strain in the structure with underfill, when the solder alloy is replaced by the intermetallic Figure Legend:

12. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Stress profiles in Si along the x-direction (the dashed line in Fig. 2, at 1.5 μm below the Si surface) for the case of soft solder joint (a) without underfill and (b) with underfill Figure Legend:

13. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Stress profiles in Si along the x-direction (the dashed line in Fig. 2, at 1.5 μm below the Si surface) for the case of intermetallic joint (a) without underfill and (b) with underfill Figure Legend:

14. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Fractional carrier mobility change in Si along the x-direction (the dashed line in Fig. 2) for the cases of (a) p-MOSFET and (b) n- MOSFET. Reference lines corresponding to the carrier mobility change of ±5% are also shown. Figure Legend:

15. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Stress profiles in Si along the x-direction (the dashed line in Fig. 2, at 1.5 μm below the Si surface) for the case of soft solder joint (a) without underfill and (b) with underfill, when all materials in the model are treated as purely elastic Figure Legend:

16. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of equivalent plastic strain in the structure without underfill, when the cooling rate is (a) 100 °C/s and (b) 1 °C/s. Here, the viscoplastic behavior of solder is considered in the modeling. Figure Legend:

17. Date of download: 6/30/2016 Copyright © ASME. All rights reserved. From: Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack J. Electron. Packag. 2015;137(2):021011-021011-11. doi:10.1115/1.4029345 Contour plots of equivalent plastic strain in the structure with underfill, when the cooling rate is (a) 100 °C/s and (b) 1 °C/s. Here, the viscoplastic behavior of solder is considered in the modeling. Figure Legend: