1. Computer Architecture Chapter (7): Input / Output
Eng. Nader Taleb

2. Input / Output Problems
Wide variety of peripherals.
Delivering different amounts of data.
At different speeds and in different formats.
All of them slower than CPU and RAM.
Need I/O modules.
An I/O module has two major functions:
1- Interface to the processor and memory via the system bus.
2- Interface to one or more peripheral devices by tailored data links.

3. External Devices
External devices are classified into three categories:
Human readable: Suitable for communicating with the computer user.
- Screen, printer, keyboard.
Machine readable: Suitable for communicating with equipment.
- Magnetic disk and tape systems, sensors and actuators.
Communication: Suitable for communicating with remote devices.
- Modem.
- Network Interface Card (NIC).

4. Block Diagram of an External Device

5. I/O Module Functions Control & Timing. - Processor Communication.
Device Communication . - Data Buffering.
Error Detection.
Example: Control and timing of the transfer of data from an external device to the processor steps:
The processor checks I/O module device status.
I/O module returns status.
If ready, CPU requests data transfer using command to module.
I/O module gets data from external device.
I/O module transfers data to the processor.

6. Cont. Processor communication involves the following:
Command decoding (READ SECTOR, SEEK track number).
Data: exchange data between CPU & I/O module over data bus.
Status reporting.
Address recognition: I/O module must recognize unique address.
Device communication (commands, status information, data).
Data buffering: The transfer rate into and out of main memory or the processor is quite high.
Error detection (paper jam, bad disk track).

7. I/O Module Structure

8. I/O Operation Techniques
Programmed.
Interrupt driven.
Direct Memory Access (DMA).

9. 1. Programmed I/O Mechanism CPU has direct control over I/O.
Sensing status / Read/write commands / Transferring data.
CPU waits for I/O module to complete operation.
Wastes CPU time
Mechanism
CPU requests I/O operation.
I/O module performs operation.
I/O module sets status bits.
CPU checks status bits periodically.
I/O module does not inform CPU directly (no interrupt).
CPU may wait or come back later.

10. I/O Commands
Control: Used to activate a peripheral and tell it what to do.
Test: Used to test various status conditions associated with an I/O module and its peripherals.
Read: Causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer.
Write: Causes the I/O module to take an item of data (byte or word) from the data bus and transmit it to the peripheral.

11. I/O Addressing and Mapping
Each device given unique identifier (Address).
CPU commands contain identifier.
Memory mapped I/O.
Devices and memory share an address space.
I/O looks just like memory read/write.
No special commands for I/O.
Large selection of memory access commands available.
Isolated I/O
Separate address spaces.
Need I/O or memory select lines.
Special commands for I/O.
Limited set.

12. 2. Interrupt Driven I/O Interrupt Processing Overcomes CPU waiting.
No repeated CPU checking of device.
I/O module interrupts when ready.
Interrupt Processing
The device issues an interrupt signal to the processor.
CPU finishes execution of the current instruction before the interrupt.
Acknowledgment signal sent by CPU which allows the device to remove its interrupt signal.
The processor prepare to transfer control to the interrupt routine. it save needed information (Status of the processor and the location of the next instruction to be executed).
When interrupt processing is complete, the saved register values are retrieved from the stack and restored to the registers.
Restore the next instruction address to be executed.

13. Design Issues 1. Device Identification:
How does the processor determine which device issued the interrupt?
If multiple interrupts have occurred, how does the processor decide which one to process?
1. Device Identification:
Four general categories of techniques are in common use:
• Multiple interrupt lines.
• Software poll.
• Daisy chain (hardware poll, vectored).
• Bus arbitration (vectored).

14. Cont. Multiple interrupt lines: Software Poll:
Dedicate few bus lines or processor pins to interrupt lines.
Each line will have multiple I/O modules attached to it. Thus, one of the other three techniques must be used on each line.
Software Poll:
Processor branches an interrupt-service routine whose job is to poll each I/O module to determine which module caused interrupt.
The disadvantage of the software poll is that it is time consuming.

15. Cont. Daisy chain or hardware poll: Bus arbitration:
Interrupt Acknowledge sent down a chain.
Module responsible places vector on bus.
CPU uses vector to identify handler routine.
Bus arbitration:
an I/O module must first gain control of the bus before it can raise the interrupt request line.
When the processor detects the interrupt, it responds on the interrupt acknowledge line. The requesting module then places its vector on the data lines.

16. 2. Multiple Interrupts
The above techniques serve to identify the requesting I/O module. They also provide a way of assigning priorities when more than one device is requesting interrupt service.
Multiple lines: the processor just picks the interrupt line with the highest priority.
Software polling: the order in which modules are polled determines their priority.
Daisy Chain: the order of modules on a daisy chain determines their priority.
Bus arbitration: it can employ a priority scheme.

17. Example: Intel 82C59A Interrupt Controller

18. 3. Direct Memory Access (DMA)
Drawback: Interrupt driven and programmed I/O require active CPU intervention.
The I/O transfer rate is limited by the speed with which the processor can test and service a device.
The processor is tied up (a number of instructions must be executed for each I/O transfer).
When large volumes of data are to be moved, a more efficient technique is required: direct memory access (DMA).

19. DMA Function DMA involves an additional module on the system bus.
The DMA module is capable of taking over control of the system from the processor to transfer data to and from memory over the system bus.
The DMA module must use the bus only when the processor does not need it, or it must force the processor to suspend operation temporarily.

20. Processor is involved only at the beginning and end of the transfer.
DMA Operation
CPU tells DMA controller the following:
Read/Write.
Device address.
Starting address of memory block for data.
Amount of data to be transferred.
The processor carries on with other work.
DMA controller deals with transfer directly to or from memory, without going through the processor.
DMA controller sends interrupt when finished.
Processor is involved only at the beginning and end of the transfer.

21. DMA Transfer Cycle DMA controller takes over bus for a cycle.
Transfer of one word of data.
Not an interrupt (CPU does not switch context).
CPU suspended just before it accesses bus.
Before an operand or data fetch or a data write.
Slows down CPU but not as much as CPU doing transfer.

22. DMA Configurations 1 Detached DMA
Each transfer uses bus twice (I/O to DMA then DMA to memory).
CPU is suspended twice.

23. Cont. 2 Integrated DMA – I/O Controller may support >1 device
Each transfer uses bus once (DMA to memory).
CPU is suspended once.

24. Cont. 3 I/O Bus Bus supports all DMA enabled devices.
Each transfer uses bus once (DMA to memory).
CPU is suspended once.

25. I/O Channels I/O devices getting more complexity.
- e.g. 3D graphics cards.
CPU instructs I/O controller to do transfer.
I/O controller does entire transfer.
Improves speed.
Takes load off CPU.
Dedicated processor is faster (I/O Processor).

26. I/O Channel Characteristics
The I/O channel represents an extension of the DMA concept.
An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations.
In a computer system with such devices, the CPU does not execute I/O instructions. Such instructions are stored in main memory to be executed by a special-purpose processor in the I/O channel itself.
The program will specify the device , the area of memory for storage, priority, and actions to be taken for certain error conditions.

27. Types of I/O Channels A selector channel
Controls multiple high-speed devices at any one time.
It is dedicated to the transfer of data with one of those devices. Thus, the I/O channel selects one device and effects the data transfer.
The I/O channel serves in place of the CPU in controlling these I/O controllers.

28. Cont. 2. A multiplexor channel
Can handle I/O with multiple devices at the same time.
For low-speed devices, a byte multiplexor accepts or transmits characters as fast as possible to multiple devices.
For example, the resultant character stream from three devices might be A1 B1 C1 A2 C2 A3 B2 C3 A4, and so on.
For high-speed devices, a block multiplexor interleaves blocks of data from several devices.

29. “Connecting devices together”.
Interfacing
“Connecting devices together”.
One major characteristic of the interface is whether it is serial or parallel.
In a parallel interface, there are multiple lines connecting the I/O module and the peripheral, and multiple bits are transferred simultaneously.
A parallel interface has traditionally been used for higher-speed peripherals, such as tape and disk.

30. Cont.
In a serial interface, there is only one line used to transmit data, and bits must be transmitted one at a time.
The serial interface has traditionally been used for printers and terminals.
With a new generation of high-speed serial interfaces, parallel interfaces are becoming much less common.

31. Point-to-Point and Multipoint Configurations
The connection between an I/O module in a computer system and external devices can be either point-to-point or multipoint
A point-to-point interface provides a dedicated line between the I/O module and the external device.
It is used in small systems (PCs, workstations), and in keyboard, printer, and external modem.
Multipoint external interfaces used to support external mass storage devices (disk and tape drives) and multimedia devices (CD-ROMs, video, audio).
These multipoint interfaces are in effect external buses, and they exhibit the same type of logic as the buses.
Now we look at two key examples: Thunderbolt and InfiniBand

32. Thunderbolt
“The most recent, and fastest, peripheral connection technology that become available for general-purpose use”
One Thunderbolt cable can manage the work previously required of multiple cables.
The technology combines data, video and audio (hard drives, RAID, video, and network interfaces).
It provides up to 10 Gbps throughput in each direction.
Thunderbolt is already a standard feature of Apple’s MacBook Pro laptop and iMac desktop computers.

33. Thunderbolt Configuration
The central element in configuration is Thunderbolt controller, which is a high-performance, cross-bar switch.
Each Thunderbolt port is capable of providing the full data transfer rate of the link in both directions with no sharing of data transmission capacity.
For internal communication, Thunderbolt controller includes one or more DisplayPort protocol adapter (monitors, laptop displays, and other graphics)
The controller also includes a PCI Express switch with up to 4 PCI Express protocol adapter ports for internal comm.
The Thunderbolt controller provides access to external devices through one or more Thunderbolt connectors.

34. Thunderbolt Configuration

35. “It is a recent I/O specification aimed at the high-end server market”
InfiniBand
“It is a recent I/O specification aimed at the high-end server market”
InfiniBand has become a popular interface for storage area networking and other large storage configurations.
InfiniBand enables servers, remote storage, and other network devices to be attached in a central fabric of switches and links.
The switch-based architecture can connect up to 64,000 servers, storage systems, and networking devices.
It replaces PCI in servers.

36. InfiniBand Architecture
Instead of a number of PCI slots
connect storage systems,
routers, and other peripheral devices

37. H.W (5)
7.7
7.9
7.17
Deadline: Sunday,

38. Thank you